Charge-scaling subtractor circuit

A subtractor circuit configured to draw a difference output node to a voltage proportional to a difference between two received binary numbers, the subtractor circuit comprising:

• a plurality of sections including a most significant (MS) section, each section of the plurality of sections having a respective local difference node and a local reset device configured to draw, in response to receiving a reset signal, the respective local difference node to ground, the local difference node of the MS section being the difference output node;
• a plurality of attenuation capacitors, each attenuation capacitor of the plurality of attenuation capacitors having first and second terminals electrically interconnected to respective local difference nodes of electrically adjacent sections of the plurality of sections;
• a first set of scaled capacitors including at least one capacitor located within each section of the plurality of sections, the first set of scaled capacitors further including a first MS capacitor located within the MS section, the first MS capacitor having an input terminal electrically connected to an MS input of a first set of inputs, each capacitor of the first set of scaled capacitors having an input terminal electrically connected to a corresponding input of the first set of inputs, an output terminal electrically connected to a respective local difference node
• a set of inverters, each inverter of the set of inverters having an input terminal electrically connected to a corresponding input of a second set of inputs, each inverter of the set of inverters further having an output terminal electrically connected to an input terminal of a corresponding capacitor of a second set of scaled capacitors;
• the second set of scaled capacitors including at least one capacitor located within each section of the plurality of sections, the second set of scaled capacitors further including a second MS capacitor located within the MS section, the second MS capacitor having an input terminal electrically connected to an output terminal of an MS inverter of the set of inverters, each capacitor of the second set of scaled capacitors having an input terminal electrically connected to a corresponding output terminal of the inverter of the set of inverters, an output terminal electrically connected to a respective local difference node;
• and
• a reference capacitor electrically connected to a reference voltage, and further electrically connected to a local difference node of a least significant (LS) section of the plurality of sections, a reference capacitor value equal to a sum of values of each of the LS scaled capacitors of the first and second sets of scaled capacitors.

A method of operating a subtractor circuit that uses charge-scaling to subtract, from a first binary number, a second binary number, the subtractor circuit fabricated within an integrated circuit (IC), the method comprising:

• resetting the subtractor circuit by drawing to a reference voltage, with a reset device of the subtractor circuit, a difference output node of the subtractor circuit;
• receiving, with a first set of inputs of the subtractor circuit, a first binary number;
• receiving, with a second set of inputs of the subtractor circuit, a second binary number;
• inverting, with a set of inverters of the subtractor circuit, the second binary number received from the second set of inputs and driving, onto a set of inverter outputs, a value of an inverted second binary number;
• and
• drawing, with first and second sets of scaled capacitors of the subtractor circuit electrically connected to the first set of inputs and to the set of inverter outputs, respectively, a difference output node of the subtractor circuit to a voltage proportional to a difference between the first and second binary numbers.