Digital phase locked loop for low jitter applications
AssigneeInternational Business Machines Corporation
InventorsJingdong Deng, Rupert Shiu Chung Ho, David Flye, Zhenrong Jin, Ramana M. Malladi
Life of this patent
Estimating the term…
Loading patent…
AssigneeInternational Business Machines Corporation
InventorsJingdong Deng, Rupert Shiu Chung Ho, David Flye, Zhenrong Jin, Ramana M. Malladi
Estimating the term…
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
A phase locked loop circuit, comprising a feedback path connecting an output of a mixed mode controlled ring oscillator to a digital path and an analog path, the mixed mode controlled ring oscillator comprises an array of selectively controllable oscillator elements arranged in a plurality of rows, and further comprising a control logic which converts a digital tuning signal from the digital path or an analog tuning signal from the analog path into a plurality of control signals going into select rows of the plurality of rows for selective control of the selectively controllable oscillator elements, wherein the digital path and the analog path modify a frequency of the mixed mode controlled ring oscillator simultaneously.
Dependencies are inferred from the claim text.