Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop

A circuit, comprising

• an input receiving a reference signal having an input frequency;
• an oscillator configured to generate an intermediate signal having a frequency configured to be equal to a geometric mean of the input frequency and a desired output frequency;
• calibration logic configured to:
• count a number of cycles of an actual frequency of the intermediate signal in one cycle of the input frequency;
• and
• generate a new loop division number by dividing a loop division number, that would produce the desired output frequency when multiplied by the input frequency, by the count;
• a locked loop circuit comprising:
• a current controlled oscillator (CCO);
• a frequency locked loop (FLL) portion coupled to the CCO, receiving as input the intermediate signal and the new loop division number, and configured to cause the CCO to generate a FLL output signal having an output frequency close to or equal to desired output frequency;
• a phase locked loop (PLL) portion coupled to the CCO and configured to cause the CCO to generate a PLL output signal having a frequency equal to the desired output frequency and having a phase locked to a phase of the reference signal.

A circuit, comprising:

• an input receiving a reference signal having an input frequency;
• an oscillator configured to generate an intermediate signal having a frequency configured to be equal to a geometric mean of the input frequency and a desired output frequency;
• a controllable oscillator;
• an oscillator control circuit configured to generate an oscillator control signal for the controllable oscillator;
• a phase locked loop (PLL) coupled to the input and to the oscillator control circuit, the PLL utilizing the controllable oscillator and controlling the oscillator control circuit to cause multiplication of the input frequency by a PLL loop division number;
• calibration logic coupled to the input and to the oscillator, the calibration logic configured to count a number of cycles of an actual frequency of the intermediate signal in the input frequency, and to generate a new loop division number by dividing the PLL loop division number by the count;
• a frequency locked loop (FLL) coupled to the calibration logic, the FLL utilizing the controllable oscillator and controlling the oscillator control circuit to cause multiplication of the frequency of the intermediate signal by a FLL loop division number;
• a switch coupling the PLL to the oscillator control circuit when the FLL achieves lock.

A method of operating a phase locked loop (PLL), comprising:

• receiving a reference signal for the PLL having a reference frequency;
• generating an intermediate reference signal having intermediate reference frequency between the reference frequency and a desired output frequency of an output signal of the PLL;
• passing the intermediate reference signal to a frequency locked loop (FLL) configured to generate an intermediate output signal having the desired output frequency, from the intermediate reference signal, thereby causing a controllable oscillator of the frequency locked loop to be set to produce the desired output frequency;
• and
• coupling the controllable oscillator of the FLL to the PLL, and activate the PLL to cause the PLL to generate the output signal as having the desired output frequency.

A method of quickening lock time of a phase locked loop (PLL) having a first loop divider value, the method comprising:

• using an oscillator to generate an intermediate reference signal having an intermediate reference frequency between a desired output frequency of an output signal of the PLL and a reference frequency of a reference signal fed to the PLL as input;
• setting an output frequency of a controllable oscillator to the desired output frequency for the output signal of the PLL using a frequency locked loop (FLL) with a second loop divider value lower than the first loop divider value, wherein the second loop divider value is set such that the intermediate reference frequency multiplied by the second loop divider value yields the desired output frequency;
• providing the intermediate reference signal to the FLL;
• coupling the controllable oscillator to the PLL;
• and
• activating the PLL and deactivating the FLL.