System related integrated circuit, apparatus and method
AssigneeSTMicroelectronics S.r.l.
InventorsFrancesco Pappalardo, Giuseppe Notarangelo
Life of this patent
Estimating the term…
Abstract
A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.
Claims20
A system comprising:
- a shift register comprising a plurality of bits and configured to receive Q input data bits, wherein Q is a positive integer based on a first signal, and wherein the plurality of bits comprises data bits, address bits, and parity bits;
- and
- a multiplexer configured to:
- receive the Q input data bits,
- select an input position of the shift register based on the first signal, and
- provide the Q input data bits to the shift register at the selected input position, wherein the shift register is configured to shift the received Q input data bits from the input position.
A system comprising:
- a register comprising a first shift register and a second shift register, the first and second shift registers comprising a plurality of bits and configured to receive Q input data bits, wherein Q is a positive integer based on a first signal, and wherein the plurality of bits comprises data bits, address bits, and parity bits;
- a first multiplexer configured to select whether to shift bits of the Q input data bits into the first shift register or the second shift register based on a second signal;
- and
- a second multiplexer configured to select an input position of the second shift register based on the first signal, wherein the second shift register is configured to shift bits of the received Q input data bits from the input position based on the first signal.
A system comprising:
- a shift register comprising 32 bits and configured to receive Q input data bits, wherein Q is equal to either 22, 25, 27, or 32 based on a first signal, and wherein the 32 bits comprises preamble bits, data bits, address bits, and parity bits;
- and
- a multiplexer configured to:
- receive the Q input data bits,
- select an input position of the shift register based on the first signal, and
- provide the Q input data bits to the shift register at the selected input position, wherein the shift register is configured to shift the received Q input data bits from the input position.
Dependencies are inferred from the claim text.