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US 10,566,976 B2Granted
Complementary logic circuit and application to thin-film hybrid electronics
AssigneeInternational Business Machines Corporation
InventorsBahman Hekmatshoartabari, Ghavam G. Shahidi
Life of this patent
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Abstract
A complementary circuit, including a logic unit comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors having a single channel type and a level shifting circuit coupled to the logic unit.
Claims8
A row driver implemented using a complementary circuit, comprising:
- a logic unit configured to provide a logic function and a digital operation comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors having a single channel conductivity type including negative threshold voltages;
- and
- a level shifting circuit coupled to the logic unit,
- wherein the pull-up and pull-down transistors are both n-channel or are both p-channel,
- wherein the level shifting circuit comprises diodes implemented by a circuitry arrangement of a heterojunction field-effect transistor (HJFET) device,
- wherein the logic unit and the level shifting circuit comprise capacitors connected in series and implemented by a circuitry arrangement of a depletion-mode MOS device, and
- wherein the depletion-mode MOS device and the HJFET device are monolithically integrated.
4 more elements
A system, comprising:
- a digital, analog or mixed-signal circuit comprising a heterojunction field-effect transistor (HJFET) device and/or a depletion-mode MOS device;
- and
- a row driver implemented using a complementary circuit coupled to the digital, analog or mixed-signal circuit, the complementary circuit including:
- a logic unit configured to provide a logic function and a digital operation comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors having a single channel conductivity type including negative threshold voltages;
- and
- a level shifting circuit coupled to the logic unit,
- wherein the pull-up and pull-down transistors are both n-channel or are both p-channel,
- wherein the level shifting circuit comprises diodes implemented by a circuitry arrangement of the heterojunction field-effect transistor (HJFET) device,
- wherein the logic unit and the level shifting circuit comprise capacitors connected in series and implemented by a circuitry arrangement of the depletion-mode MOS device, and
- wherein the depletion-mode MOS devices and the HJFET devices are monolithically integrated.
7 more elements
An active matrix display, comprising:
- a row driver implemented using a complementary circuit, the complementary circuit including:
- a logic unit configured to provide a logic function and a digital operation comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors having a single channel conductivity type including negative threshold voltages;
- and
- a level shifting circuit coupled to the logic unit,
- wherein the pull-up and pull-down transistors are both n-channel or are both p-channel,
- wherein the level shifting circuit comprises diodes implemented by a circuitry arrangement of the heterojunction field-effect transistor (HJFET) device,
- wherein the logic unit and the level shifting circuit comprise capacitors connected in series and implemented by a circuitry arrangement of the depletion-mode MOS device, and
- wherein the depletion-mode MOS devices and the HJFET devices are monolithically integrated.
5 more elements
Dependencies are inferred from the claim text.