Analog power-up reset circuit for logic level reset

An electrical reset circuit configured to generate a reset pulse, comprising:

• a first device electrically connected between a power supply input and a first node, wherein the first device is configured to conduct current after the power supply input reaches a first voltage threshold;
• a first resistor electrically connected between the first node and a common node;
• a second device electrically connected between the power supply input and a second node, wherein the second device is configured to conduct current after the power supply input reaches a second voltage threshold;
• a first capacitor electrically connected between the second node and the common node;
• a second resistor electrically connected in parallel with the first capacitor;
• a first transistor electrically connected between a power rail and the common node, wherein the gate of the first transistor is electrically connected to the first node;
• and
• a second transistor electrically connected between the first node and the common node, wherein the gate of the second transistor is electrically connected to the second node.