Output driver, and semiconductor memory device and memory system having the same

A semiconductor memory device comprising:

• a command and address generator configured to decode an inverted chip selection signal and a command signal included in a command and address to generate a write command or a read command, and generate an address signal included in the command and address as a row address or a column address;
• a latency control signal generator configured to generate an on-die termination enable signal, which is activated using a value of a write latency and inactivated using the value of the write latency and a value of a burst length in response to the write command, and generate a read control signal, which is activated using a value of a read latency and inactivated using the value of the read latency and the value of the burst length in response to the read command;
• a memory cell array comprising a plurality of memory cells and configured to receive or output data from/to memory cells selected in response to the row address and the column address;
• an on-die termination controller configured to receive a first on-die termination control code to generate a first on-die termination control signal in response to the write command and the on-die termination enable signal;
• a pre-driver configured to be enabled in response to the read control signal, and generate a driver control code as a pull-up control signal or a pull-down control signal in response to data which is output from the memory cell array;
• and
• a main driver comprising a pull-up n-channel metal-oxide-semiconductor (NMOS) driver and a pull-down NMOS driver,
• wherein the pull-up NMOS driver is configured to generate high-level output data in response to the pull-up control signal, or terminate high-level input data with a first high voltage which is lower than or equal to an output power supply voltage and terminate low-level input data with a first low voltage between the first high voltage and a ground voltage, in response to the first on-die termination control signal, and
• the pull-down NMOS driver is configured to generate low-level output data in response to the pull-down control signal.

A memory system comprising:

• a first inverted chip selection signal line, a second inverted chip selection signal line, a command and address line, and a data line configured to transmit a first inverted chip selection signal, a second inverted chip selection signal, a command and address, and data, respectively;
• a first memory configured to receive the first inverted chip selection signal and the command and address, and receive or output the data;
• and
• a second memory configured to receive or output the second inverted chip selection signal, the command and address, and the data,
• wherein each of the first memory and the second memory comprises:
• a command and address generator configured to decode the first inverted chip selection signal or the second inverted chip selection signal and a command signal included in the command and address to generate a write command or a read command, and generate an address signal included in the command and address as a row address or a column address,
• a latency control signal generator configured to generate an on-die termination enable signal, which is activated using a value of a write latency and inactivated using the value of the write latency and a value of a burst length in response to the write command, and generate a read control signal, which is activated using a value of a read latency and inactivated using the value of the read latency and the value of the burst length in response to the read command,
• a memory cell array comprising a plurality of memory cells and configured to receive or output data from/to memory cells selected in response to the row address and the column address,
• an on-die termination controller configured to receive a first on-die termination control code to generate a first on-die termination control signal in response to the write command and the on-die termination enable signal,
• a pre-driver configured to be enabled in response to the read control signal receive a driver control code to generate a pull-up control signal or a pull-down control signal in response to data which is output from the memory cell array, and
• a main driver comprising a pull-up n-channel metal-oxide-semiconductor (NMOS) driver and a pull-down NMOS driver,
• wherein the pull-up NMOS driver is configured to generate high-level output data in response to the pull-up control signal, or terminate high-level input data with a first high voltage which is lower than or equal to an output power supply voltage and terminate low-level input data with a first low voltage between the first high voltage and a ground voltage, in response to the first on-die termination control signal, and
• the pull-down NMOS driver is configured to generate low-level output data in response to the pull-down control signal.