Sense amplifier flip-flop and method for fixing setup time violations in an integrated circuit

A method for fixing setup time violations in an integrated circuit (IC) design using a sense amplifier flip-flop (SAFF), wherein the SAFF includes a master latch coupled to a slave latch, wherein the master latch includes a sense amplifier and the SAFF is configured with an equal number of p-type metal oxide semiconductor (PMOS) transistors and n-type metal oxide semiconductor (NMOS) transistors configured to reduce a block area of the IC, the method comprising:

• receiving a clock signal;
• generating an inverted clock signal from the clock signal which transitions from a low logic level to a high logic level when a clock signal transitions from a high logic level to a low logic level;
• receiving a data signal;
• applying the data signal to the sense amplifier when the clock signal is at the low logic level, wherein a portion of the sense amplifier is responsive to the inverted clock signal;
• storing a value of the data signal in the slave latch when the clock signal transitions from the low logic level to the high logic level;
• and
• providing an output signal from the slave latch.

A clocked data circuit comprising:

• a first data stage;
• a second data stage;
• a first latch buffer including a first buffer input, wherein an output of the first latch buffer is coupled to a first controlling node;
• a second latch buffer including a second buffer input, wherein an output of the second latch buffer is coupled to a second controlling node;
• a first clock stage coupled to an input of the first latch buffer;
• a second clock stage coupled to an input of the second latch buffer;
• a sense amplifier;
• and
• a slave latch,
• wherein the first data stage is coupled to a first input of the sense amplifier, the first input of the sense amplifier being the first controlling node,
• wherein the second data stage is coupled to a second input of the sense amplifier, the second input of the sense amplifier being the second controlling node, and
• wherein each of the first controlling node and the second controlling node is configured to be pre-charged by the first clock stage and the second clock stage, respectively, when a clock signal is a low level.