Current-mode logic latches for a PVT-robust mod 3 frequency divider

An integrated circuit on a semiconductor substrate, the integrated circuit including a modified digital latch that comprises:

• an input transistor arrangement that includes:
• a first input transistor having a base capacitively coupled to receive a first input signal;
• a second input transistor having a base capacitively coupled to receive a second input signal;
• and
• a complementary transistor having a base capacitively coupled to a fixed voltage node, the input transistor arrangement producing a differential output voltage between output nodes when a clock signal is asserted, the differential output voltage representing a logical NOR of the first and second input signals;
• a cross-coupled transistor pair (“latch pair”) coupled to the output nodes to latch the differential output voltage when the clock signal is de-asserted;
• a differential transistor pair (“clock pair”) that, responsive to the clock signal, steers a bias current between a shared emitter node of the track pair and a shared emitter node of the latch pair;
• and
• a matched set of bias transistors each having a base coupled by a respective base resistance to a shared bias voltage node, the matched set including:
• a first bias transistor that determines the bias current for the clock pair;
• and
• a second bias transistor that sources or sinks an equal bias current through a load resistance to determine a reference voltage on a reference voltage node,
• the reference voltage node being coupled to a base of each transistor in the input transistor arrangement by a bias resistance proportional to each of said base resistances to provide a bias voltage.

A method of manufacturing a digital latch, the method comprising:

• capacitively coupling bases of a differential transistor pair (“track pair”) to a differential input signal to cause a differential output voltage between output nodes to track the differential input signal when a clock signal is asserted;
• connecting a cross-coupled transistor pair (“latch pair”) to the output nodes to latch the differential output voltage when the clock signal is de-asserted;
• providing a differential transistor pair (“clock pair”) that, responsive to the clock signal, steers a bias current between a shared emitter node of the track pair and a shared emitter node of the latch pair;
• and
• biasing with a matched set of bias transistors each having a base coupled by a respective base resistance to a shared bias voltage node, the matched set including:
• a first bias transistor that determines the bias current for the clock pair;
• and
• a second bias transistor that sources or sinks an equal bias current through a load resistance to determine a reference voltage on a reference voltage node,
• the reference voltage node being coupled to a base of each transistor in the track pair by a bias resistance proportional to each of said base resistances to provide a bias voltage.