Integrated circuit and method of manufacturing integrated circuit
AssigneeRohm Co., Ltd.
InventorsNaohiro Nomura, Sachito Horiuchi, Kunihiko Iwamoto
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Abstract
An integrated circuit having a plurality of miniaturized transistors, wherein the plurality of transistors include: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration.
Claims32
An integrated circuit comprising:
- a plurality of miniaturized transistors, the plurality of miniaturized transistors including:
- high concentration transistors which include channel regions having impurity concentrations of a first concentration;
- and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration,
- wherein the low concentration transistors are used for transistors which are more likely to be affected by a 1/f noise of the integrated circuit, among the plurality of transistors, than the high concentration transistors.
An integrated circuit comprising:
- a plurality of miniaturized transistors, the plurality of miniaturized transistors including:
- high concentration transistors which include channel regions having impurity concentrations of a first concentration;
- and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration;
- and
- an operational amplifier,
- wherein the operational amplifier includes a differential pair, and
- wherein transistors constituting the differential pair are the low concentration transistors among the plurality of transistors.
An integrated circuit comprising:
- a plurality of miniaturized transistors, the plurality of miniaturized transistors including:
- high concentration transistors which include channel regions having impurity concentrations of a first concentration;
- and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration,
- wherein the plurality of transistors includes:
- buried channel type MOSFETs;
- and surface channel type MOSFETs, and
- wherein the buried channel type MOSFETs are used for transistors which are more likely to be affected by the 1/f noise of the integrated circuit than the surface channel type MOSFETs.
A method of manufacturing an integrated circuit including a plurality of transistors including a first transistor and a second transistor which are miniaturized, the method comprising:
- selectively performing an ion implantation such that impurity ions are implanted into a region where the first transistor is formed while no impurity ions are implanted into a region where the second transistor is formed in a semiconductor substrate, to form a first channel region in the region where the first transistor is formed;
- and
- selectively performing an ion implantation such that impurity ions are implanted into the region where the second transistor is formed while no impurity ions are implanted into the region where the first transistor is formed in the semiconductor substrate, to form a second channel region in the region where the second transistor is formed,
- wherein an impurity concentration of the first channel region is set lower than an impurity concentration of the second channel region,
- wherein the integrated circuit includes an operational amplifier,
- wherein the operational amplifier includes a differential pair,
- wherein the first transistor includes transistors constituting the differential pair, and
- wherein the first channel region includes channel regions of the transistors constituting the differential pair.
Dependencies are inferred from the claim text.