Methods and systems of operating buck-boost converters

A power converter comprising:

• a buck field effect transistor (FET) defining a gate, a drain, and a source, the drain coupled to an input voltage;
• an inductor defining a first lead and a second lead, the first lead coupled to the source of the buck FET;
• a boost FET defining a gate, a drain, and a source, the drain of the boost FET coupled to the second lead of the inductor, and the source of the boost FET coupled to a ground;
• a feedback sensor defining a feedback output, the feedback sensor coupled between a voltage output of the power converter and the second lead of the inductor, the feedback sensor configured to sense a voltage or a current supplied by the power converter to a load;
• a current sensor defining a current sense output, the current sensor configured to sense current through the inductor and produce a current sense signal on the current sense output;
• a controller defining a current sense input, a feedback sense input, a buck gate output, and a boost gate output, the current sense input coupled to the current sense output, the feedback sense input coupled to the feedback output, the buck gate output coupled to the gate of the buck FET, and the boost gate output coupled to the gate of the boost FET;
• the controller comprising:
• an oscillator circuit configured to generate a buck clock signal at a switching frequency, and configured to generate a boost clock signal at the switching frequency, the boost clock signal having a phase difference from the buck clock signal;
• an error amplifier defining the feedback sense input and an error output, the feedback sense input coupled to the feedback output of the feedback sensor, the error amplifier configured to sense a feedback signal on the feedback sense input and produce an error signal on the error output, the error signal proportional to the feedback signal;
• a buck circuit, the buck circuit configured to assert the buck gate output based on assertion of the buck clock signal, and then de-assert the buck gate output if the current sense signal reaches a first peak current value;
• and
• a boost circuit, the boost circuit configured to assert the boost gate output based on assertion of the boost clock signal if the error signal is above a first predetermined threshold, and then de-assert the boost gate output when the current sense signal reaches a second peak current value.

A driver integrated circuit (IC) for a buck-boost converter, comprising:

• a supply voltage terminal, a switch node terminal, a boost gate terminal, and a feedback terminal;
• a buck field effect transistor (FET) defining a gate, a source, and a drain, the drain coupled to the supply voltage terminal, and the source coupled to the switch node terminal;
• a current sensor defining a current sense output, the current sensor associated with the buck FET, and the current sensor configured to generate a current sense signal proportional to current through the buck FET;
• a controller defining a current sense input, a feedback sense input, a buck gate output, and a boost gate output, the current sense input coupled to the current sense signal, the feedback sense input coupled to the feedback terminal, the buck gate output coupled to the gate of the buck FET, and the boost gate output coupled to the boost gate terminal;
• the controller comprising:
• an oscillator circuit configured to generate a buck clock signal at a switching frequency, and generate a boost clock signal at the switching frequency, the boost clock signal having a phase difference from the buck clock signal;
• an error amplifier defining the feedback sense input and an error output, the error amplifier configured to sense a feedback signal on the feedback terminal and produce an error signal on the error output, the error signal proportional to the feedback signal;
• a buck circuit, the buck circuit configured to assert the gate of the buck FET based on assertion of the buck clock signal, and then de-assert the gate of the buck FET if the current sense signal reaches a first peak current value;
• and
• a boost circuit, the boost circuit configured to assert the boost gate terminal based on assertion of the boost clock signal if the error signal is above a first predetermined threshold, and then de-assert the boost gate terminal when the current sense signal reaches a second peak current value.