Stacked memory package incorporating millimeter wave antenna in die stack
AssigneeMicron Technology, Inc.
InventorsJohn F. Kaeding, Owen R. Fay
Life of this patent
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Abstract
A stacked semiconductor device assembly may include a first semiconductor device having a first substrate and a first set of vias through the first substrate. The first set of vias may define a first portion of an antenna structure. The stacked semiconductor device assembly may further include a second semiconductor device having a second substrate and a second set of vias through the second substrate. The second set of vias may define a second portion of the antenna structure. The stacked semiconductor device assembly may also include a stack interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna.
Claims20
A stacked semiconductor device assembly comprising:
- a first semiconductor device having a first substrate and a first set of vias through the first substrate, the first set of vias defining a first portion of an antenna structure;
- a second semiconductor device having a second substrate and a second set of vias through the second substrate, the second set of vias defining a second portion of the antenna structure;
- and
- a stack interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.
A method comprising:
- forming a first set of vias through a first substrate of a first semiconductor device, the first set of vias defining a first portion of an antenna structure;
- forming a second set of vias through a second substrate of a second semiconductor device, the second set of vias defining a second portion of the antenna structure;
- and
- electrically coupling the first portion of the antenna structure to the second portion of the antenna by a stack interconnect structure.
A stacked three-dimensional integrated circuit apparatus comprising:
- a first semiconductor device having a first substrate;
- a second semiconductor device having a second substrate;
- and
- an antenna structure extending along a vertical surface of the stacked three-dimensional integrated circuit apparatus, the antenna structure defined by at least a first set of vias through the first substrate and a second set of vias through the second substrate.
Dependencies are inferred from the claim text.