Probability-based optimization of system on chip (SOC) power
AssigneeSeagate Technology LLC
InventorsNitin Kumar Chhabra, Rohit Halba, Shashi Kumar Shaw, Shrikrishna Nana Mehetre
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Abstract
A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.
Claims20
A method of designing a system on chip (SoC), comprising:
- for a total number of bits N of the SoC, calculating a minimum number of bits NP of the total number of bits N that can simultaneously switch states without producing an error across a complete warranty time period of the SoC;
- carrying out power estimation calculations for the SoC using the calculated minimum number of bits NP;
- and
- providing a power consumption value for the SoC based on an average power value for the minimum number of bits NP, to allow configuration of a power supply to be used in a system employing the SoC.
A method comprising:
- determining a number of channels to be employed in a system on chip (SoC), each channel of the number of channels including a number of bits per channel;
- determining a total number of bits N for the SoC based on the number of channels and based on the number of bits per channel;
- receiving warranty information for the SoC;
- calculating, based on the total number of bits N and the warranty information, a minimum number of bits NP of the total number of bits N that can simultaneously switch states without producing an error across a complete warranty time period of the SoC;
- and
- providing a power consumption value for the SoC based on a current consumption of the minimum number of bits NP that can simultaneously switch states without producing an error across the complete warranty time period of the SoC, to allow configuration of a power supply to be employed in a system employing the SoC.
A non-transitory computer-readable storage medium having encoded therein computer-executable instructions for causing a computing system programmed thereby to perform a method comprising:
- for a system on chip (SoC) having a total number of bits N, calculating a minimum number of bits NP of the total number of bits N that can simultaneously switch states without producing an error across a complete warranty time period of the SoC;
- carrying out power estimation calculations for the SoC using the calculated minimum number of bits NP;
- and
- setting an average power value for the SoC based on an average power value for the minimum number of bits NP;
- and
- providing a power consumption value for the SoC based on the average power value for the minimum number of bits NP, to allow configuration of a power supply to be used in a system employing the SoC.
Dependencies are inferred from the claim text.