# US 10,554,453 B1 · Quarter-rate charge-steering decision feedback equalizer (DFE)

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- Number: US 10,554,453 B1
- Document ID: US10554453B1
- Status: Granted
- Kind: B1
- Application number: 16/379,502
- Filed: 2019-04-09
- Granted: 2020-02-04
- Earliest claimed: 2019-04-09
- Assignees: Ciena Corporation
- Applicants: Mahdi Parvizi; Jacob Pike; Naim Ben-Hamida; Sadok Aouini; Calvin Plett
- Inventors: Mahdi Parvizi; Jacob Pike; Naim Ben-Hamida; Sadok Aouini; Calvin Plett
- Web page: https://patentgrep.com/patent/US10554453B1

## CPC

- H04L 25/03063: {using fractionally spaced delay lines or combinations of fractionally and integrally spaced taps}
- H04L 25/03146: {with a recursive structure (H04L25/03127 takes precedence)}
- H03K 3/356: Bistable circuits
- H04L 2025/03509: {fractionally spaced (H04L2025/03515 takes precedence)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A decision feedback equalizer (DFE) comprises four charge-steering (CS) primary latches and four primary taps. Two of the four CS primary latches are driven by complementary in-phase quarter-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature quarter-rate clocks. No element of the DFE is driven by any half-rate clocks. In some implementations, each of the primary latches including a respective differential pair of n-channel output transistors and each primary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS primary latches. In other implementations, each of the primary latches including a respective differential pair of p-channel input transistors and each primary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS primary latches.

## Claims

### Claim 1

A decision feedback equalizer (DFE) comprising:
four charge-steering (CS) primary latches, each of the primary latches including a respective differential pair of n-channel output transistors; and
four primary taps,
wherein two of the four CS primary latches are driven by complementary in-phase ¼-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature ¼-rate clocks,
wherein each primary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS primary latches, and
wherein no element of the DFE is driven by any ½-rate clock.

### Claim 2 (depends on 1)

The DFE as recited in claim 1, further comprising:
four circuits to demultiplex an input data stream into four input data streams such that the first input data stream overlaps the second input data stream by 50%, the second input data stream overlaps the third input data stream by 50%, the third input data stream overlaps the fourth input data stream by 50%, and the fourth input data stream overlaps the first input data stream by 50%.

### Claim 3 (depends on 2)

The DFE as recited in claim 2, wherein each of the four circuits is a simple switch driven by a respective one of the ¼-rate clocks.

### Claim 4 (depends on 2)

The DFE as recited in claim 2, wherein each of the four circuits is a track-and-hold circuit.

### Claim 5 (depends on 2)

The DFE as recited in claim 2, wherein for each primary tap the respective differential pair of p-channel input transistors are connected via their drain nodes to a differential representation of a bit value provided by a respective one of the four input data streams.

### Claim 6 (depends on 1)

The DFE as recited in claim 1, wherein for each primary tap the respective differential pair of p-channel input transistors are connected via their drain nodes to a different respective one of the four CS primary latches.

### Claim 7 (depends on 1)

The DFE as recited in claim 1, wherein every switch of at least one of the primary taps is driven by one of the ¼-rate clocks.

### Claim 8 (depends on 2)

The DFE as recited in claim 2, further comprising:
four CS secondary latches, each of the secondary latches including a respective differential pair of n-channel output transistors; and
four secondary taps,
wherein two of the four CS secondary latches are driven by the complementary in-phase ¼-rate clocks and the other two of the four CS secondary latches are driven by the complementary quadrature ¼-rate clocks, and
wherein each secondary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS secondary latches.

### Claim 9 (depends on 8)

The DFE as recited in claim 8, wherein for each secondary tap the respective differential pair of p-channel input transistors are connected via their drain nodes to a differential representation of a bit value provided by a respective one of the four input data streams.

### Claim 10 (depends on 8)

The DFE as recited in claim 8, wherein for each secondary tap the respective differential pair of p-channel input transistors are connected via their drain nodes to a different respective one of the four CS primary latches.

### Claim 11

A decision feedback equalizer (DFE) comprising:
four charge-steering (CS) primary latches, each of the primary latches including a respective differential pair of p-channel input transistors; and
four primary taps,
wherein two of the four CS primary latches are driven by complementary in-phase ¼-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature ¼-rate clocks,
wherein each primary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS primary latches, and
wherein no element of the DFE is driven by any ½-rate clock.

### Claim 12 (depends on 11)

The DFE as recited in claim 11, further comprising:
four circuits to demultiplex an input data stream into four input data streams such that the first input data stream overlaps the second input data stream by 50%, the second input data stream overlaps the third input data stream by 50%, the third input data stream overlaps the fourth input data stream by 50%, and the fourth input data stream overlaps the first input data stream by 50%.

### Claim 13 (depends on 12)

The DFE as recited in claim 12, wherein each of the four circuits is a simple switch driven by a respective one of the ¼-rate clocks.

### Claim 14 (depends on 12)

The DFE as recited in claim 12, wherein each of the four circuits is a track-and-hold circuit.

### Claim 15 (depends on 12)

The DFE as recited in claim 12, wherein for each primary tap the respective differential pair of n-channel output transistors are connected via their source nodes to a differential representation of a bit value provided by a respective one of the four input data streams.

### Claim 16 (depends on 11)

The DFE as recited in claim 11, wherein for each primary tap the respective differential pair of n-channel output transistors are connected via their source nodes to a different respective one of the four CS primary latches.

### Claim 17 (depends on 11)

The DFE as recited in claim 11, wherein every switch of at least one of the primary taps is driven by one of the ¼-rate clocks.

### Claim 18 (depends on 12)

The DFE as recited in claim 12, further comprising:
four CS secondary latches, each of the secondary latches including a respective differential pair of p-channel input transistors; and
four secondary taps,
wherein two of the four CS secondary latches are driven by the complementary in-phase ¼-rate clocks and the other two of the four CS secondary latches are driven by the complementary quadrature ¼-rate clocks, and
wherein each secondary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS secondary latches.

### Claim 19 (depends on 18)

The DFE as recited in claim 18, wherein for each secondary tap the respective differential pair of n-channel output transistors are connected via their source nodes to a differential representation of a bit value provided by a respective one of the four input data streams.

### Claim 20 (depends on 18)

The DFE as recited in claim 18, wherein for each secondary tap the respective differential pair of n-channel output transistors are connected via their source nodes to a different respective one of the four CS primary latches.