A magnetic domain wall type analog memory, comprising:
- a plurality of magnetic domain wall type analog memory elements;
- a first transistor element;
- a second transistor element;
- and
- a plurality of third transistor elements as cell selection control elements,
- wherein, each of the magnetic domain wall type analog memory elements comprising:
- a magnetization fixed layer in which a magnetization is oriented in a first direction;
- a non-magnetic layer provided on one surface of the magnetization fixed layer;
- a magnetic domain wall drive layer including a first area in which a magnetization is oriented in the first direction, a second area in which a magnetization is oriented in a second direction opposite to the first direction, and a magnetic domain wall formed as an interface between the first area and the second area and provided to sandwich the non-magnetic layer between the magnetic domain wall drive layer and the magnetization fixed layer;
- a current controller configured to cause a current to flow between the magnetization fixed layer and the second area at the time of reading;
- and
- a first magnetization supplier configured to supply a magnetization oriented in the first direction to the first area in the magnetic domain wall drive layer and a second magnetization supplier configured to supply a magnetization oriented in the second direction to the second area in the magnetic domain wall drive layer,
- wherein a magnetization of the first magnetization supplier is oriented in the first direction and a magnetization of the second magnetization supplier is oriented in the second direction,
- wherein, a first wiring connects each of the magnetization fixed layers in the plurality of the magnetic domain wall type analog memory elements to the first transistor element,
- wherein, a second wiring connects each of the first magnetization suppliers in the plurality of magnetic domain wall type analog memory elements to the second transistor element, and
- wherein, each of the second magnetization suppliers in the plurality of magnetic domain wall type analog memory elements is connected by one of a plurality of third wirings to a respective one of the plurality of third transistor elements.