Deskew circuit for automated test systems
AssigneeAnalog Devices, Inc.
InventorsAndrew Nathan Mort, Christopher C. McQuilkin
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Abstract
This disclosure is in the field of electronics and more specifically in the field of timing control electronics. In an example, a timing control system can include or use an array of circuit cells, and each cell can provide a signal delay using a fixed delay or interpolation. The interpolation can include, in one or more cells, using three timing signals with substantially different delays to create a delayed output signal. Linearity of the delayed output signal is thereby improved. In an example, an impedance transformation circuit can be applied to improve a bandwidth in one or more of the cells to thereby improve the bandwidth of the timing control system.
Claims21
A deskew system for providing a programmable delay, the system comprising:
- multiple delay cells coupled in a series, wherein a first cell of the multiple delay cells includes a first input node and a first output node, and the first cell is configured to provide a maximum, minimum, or intermediate delay to an input signal at the first input node, and wherein the first cell includes:
- an early signal input node coupled to a forward output node of a preceding cell in the series or to the first input node;
- a mid signal input node;
- a late signal input node coupled to a reverse output node of a subsequent cell in the series;
- and
- a summing circuit configured to provide a delayed output signal at the first output node by combining signals that are respectively modulated according to a delay adjust code and respective command signals at the early, mid, and late signal input nodes;
- wherein the delay adjust code indicates a delay amount to apply to the input signal.
An apparatus coupled between an input node and an output node for delaying an electrical signal received at the input node and providing a corresponding delayed signal at the output node, the apparatus comprising:
- a current splitter coupled to a current source and configured to provide respective portions of a source current signal to at least first, second, and third current signal paths, wherein each of the first, second, and third current signal paths is enabled by an early timing signal, a late timing signal;
- and an intermediate timing signal, respectively, to conduct its respective portion of the source current signal;
- wherein the early timing signal is based on the electrical signal received at the input node;
- wherein the late timing signal is based on the electrical signal received at the input node and a first delay;
- wherein the intermediate timing signal is based on the electrical signal received at the input node and a different second delay;
- wherein a timing of the delay signal provided at the output node is based on the early, late, and intermediate timing signals;
- and
- an impedance transformer circuit coupled between the output node and the first, second, and. third current signal paths, wherein the impedance transformer circuit is configured to reduce an impedance characteristic of the output node.
A method for providing a programmable delay signal, the method comprising:
- receiving an input control signal to be delayed at a forward input node of a first deskew cell in a series of deskew cells, wherein the first deskew cell is configured to provide a first delayed output control signal;
- receiving a delay adjust code indicative of a specified delay amount;
- apportioning a source signal to first, second, and/or third signal paths in the first deskew cell based on the delay adjust code to provide a minimum delay, maximum delay, or intermediate delay, respectively;
- based on at least one control signal from an adjacent cell in the series of deskew cells, modulating signals in one or more of the first, second, and third signal paths;
- and
- combining signals from the first, second, and third signal paths to provide the output control signal at an output node.
Dependencies are inferred from the claim text.