High speed data transfer
AssigneeBAE Systems Information and Electronic Systems Integration Inc.
InventorsKevin S. Bassett, Wojciech J. Krawiec
Life of this patent
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Abstract
The system can utilize a standard high speed FPGA interface for a non-traditional use to facilitate the processing of high amounts of streaming digital data or the method can be implemented in other high speed data transfer systems. This system and method include the use of training/calibration pattern techniques implemented in a FPGA, or other system, to calibrate numerous multi-arm demultiplexers. The training/calibration sequence data rate being slower than the input data rate. In one example, the system and method utilized a mono-bit receiver capable of digitizing signals of at least 40 GHz with at least 20 GHz of instantaneous bandwidth.
Claims15
A system for high-speed data transfer comprising:
- a pattern generator module configured to provide calibration sequence data that is transmitted to a 1:M demultiplexer via a transmitter at a transmitting rate, the transmitter being internal to a field programmable gate array;
- the 1:M demultiplexer being configured to receive a system input data stream and produce a plurality of serial data streams, the plurality of serial data streams having a data rate that is faster than the transmitter rate;
- a plurality of receivers for receiving the plurality of serial data streams from the 1:M demultiplexer, the plurality of receivers being internal to the field programmable gate array;
- and
- a synchronization module configured to change a phase of a calibration sequence transmit clock to move the calibration sequence data, in time, relative to a system input sampling clock, thereby facilitating high-speed data transfer.
A method of calibrating a high-speed data transfer system comprising:
- providing a high-speed data transfer system having a calibration sequence data rate slower than an input sample data rate;
- and
- changing a phase of a calibration sequence transmit clock with enough resolution to move, in time, the calibration sequence data relative to a system input sampling clock edge such that the resolution is less than a period of the system input sampling clock.
Dependencies are inferred from the claim text.