Network processors

A network processor comprising:

• a packet processor grid comprising a plurality of packet processors;
• a dispatcher configured to provide a plurality of packet descriptors from a linked list to the plurality of packet processors to process the plurality of packet descriptors, wherein the dispatcher is further configured to store the plurality of packet descriptors in the linked list based on an order in which the plurality of packet descriptors are received by the dispatcher;
• accelerator circuits configured to perform hardware based acceleration of packet processing tasks on behalf of the plurality of packet processors to process the plurality of packet descriptors, wherein the accelerator circuits are implemented in a different clock domain than the plurality of packet processors and are accessed by the plurality of packet processors via a communication bus;
• and
• a reorderer configured to receive the plurality of packet descriptors from the plurality of packet processors after the plurality of packet descriptors have been processed and store each of the plurality of packet descriptors in a same position in the linked list in which the packet descriptor was stored by the dispatcher,
• wherein the reorderer is further configured to provide processed packet descriptors from the linked list as an output until a head of the linked list is empty.

A network processor comprising:

• a packet processor grid comprising a plurality of packet processors;
• a dispatcher configured to provide a plurality of packet descriptors from a linked list to the plurality of packet processors to process the plurality of packet descriptors;
• accelerator circuits configured to perform hardware based acceleration of packet processing tasks on behalf of the plurality of packet processors to process the plurality of packet descriptors, wherein the accelerator circuits are implemented in a different clock domain than the plurality of packet processors and are accessed by the plurality of packet processors via a communication bus;
• and
• a queue manager configured to queue one of the plurality of packet descriptors, processed by one of the plurality of packet processors, in an egress queue for transmission, wherein the queue manager is further configured to move a packet payload associated with the one of the plurality of packet descriptors from an internal memory of the network processor to an external memory of the network processor based on one or more conditions associated with the network processor.

A method comprising:

• receiving a plurality of packet descriptors;
• storing the plurality of packet descriptors in a linked list based on an order in which the plurality of packet descriptors are received;
• providing each of the plurality of packet descriptors from the linked list to one of a plurality of packet processors based on utilizations of the plurality of packet processors;
• sending, a subset of the plurality of packet descriptors, from one or more of the plurality of packet processors to accelerator circuits to perform hardware based acceleration of packet processing tasks on behalf of the one or more of the plurality of packet processors to process the subset of the plurality of packet descriptors;
• storing each of a plurality of processed packet descriptors in a same position in the linked list in which a corresponding packet descriptor was stored before being processed by the one of the plurality of packet processors;
• and
• providing the plurality of processed packet descriptors from the linked list as output until a head of the linked list is empty,
• wherein the accelerator circuits are implemented in a different clock domain than the plurality of packet processors and are accessed by the plurality of packet processors via a communication bus.

A network processor comprising:

• a packet processor grid comprising a plurality of packet processors;
• a dispatcher configured to receive a plurality of packet descriptors, store the plurality of packet descriptors in a linked list based on an order in which the plurality of packet descriptors are received by the dispatcher, and provide each of the plurality of packet descriptors from the linked list to one of the plurality of packet processors based on utilizations of the plurality of packet processors;
• accelerator circuits configured to perform hardware based acceleration of packet processing tasks on behalf of the plurality of packet processors to process the plurality of packet descriptors, wherein the accelerator circuits are implemented in a different clock domain than the plurality of packet processors and are accessed by the plurality of packet processors via a communication bus;
• and
• a reorderer configured to receive a plurality of processed packet descriptors from the plurality of packet processors, store each of the plurality of processed packet descriptors in a same position in the linked list in which a corresponding packet descriptor was stored by the dispatcher, and provide the plurality of processed packet descriptors from the linked list as output until a head of the linked list is empty.