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US 10,541,897 B2Granted
Mismatch compensation at differential signal receiver
AssigneeWestern Digital Technologies, Inc.
InventorVinay Siddaiah
Life of this patent
Estimating the term…
Abstract
A non-volatile memory module includes an input/output buffer coupled to first and second signal transmission paths, and control circuitry coupled to the input/output buffer, the control circuitry being configured to receive a first signal on the first signal transmission path, receive a second signal on the second signal transmission path, determine a delay between the first signal and the second signal, generate a delay mismatch value based on the determined delay, and transmit the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer.
Claims21
A non-volatile memory module comprising:
- an input/output buffer coupled to first and second signal transmission paths;
- and
- control circuitry coupled to the input/output buffer, the control circuitry being configured to:
- receive a first signal on the first signal transmission path from a controller chip communicatively coupled to the non-volatile memory module;
- receive a second signal on the second signal transmission path from the controller chip;
- determine a delay between the first signal and the second signal;
- generate a delay mismatch value based on the determined delay;
- transmit, to the controller chip, the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer;
- receive a true signal of a complementary signal pair on the first signal transmission path;
- and
- receive a complementary signal of the complementary signal pair on the second signal transmission path;
- wherein one of the true signal and the complementary signal is delayed in accordance with the delay mismatch value.
9 more elements
A method operational in a non-volatile memory module for compensating for a delay mismatch in signal transmission paths, the method comprising:
- receiving, at an input/output buffer of the non-volatile memory module, a first signal on a first signal transmission path from a controller chip communicatively coupled to the non-volatile memory module;
- receiving, at the input/output buffer of the non-volatile memory module, a second signal on a second signal transmission path from the controller chip;
- determining a delay between the first signal and the second signal;
- generating a delay mismatch value based on the determined delay;
- transmitting, to the controller chip, the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer;
- receiving a true signal of a complementary signal pair on the first signal transmission path;
- and
- receiving a complementary signal of the complementary signal pair on the second signal transmission path;
- wherein one of the true signal and the complementary signal is delayed in accordance with the delay mismatch value.
6 more elements
A computing device comprising:
- an input/output buffer coupled to first and second signal transmission paths;
- and
- control circuitry coupled to the input/output buffer, the control circuitry being configured to:
- receive a first signal on the first signal transmission path from a computing module communicatively coupled to the computing device;
- receive a second signal on the second signal transmission path from the computing module;
- determine a delay between the first signal and the second signal;
- generate a delay mismatch value based on the determined delay;
- transmit, to the computing module, the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer;
- receive a true signal of a complementary signal pair on the first signal transmission path;
- and
- receive a complementary signal of the complementary signal pair on the second signal transmission path;
- wherein one of the true signal and the complementary signal is delayed in accordance with the delay mismatch value.
9 more elements
A non-volatile memory module comprising:
- an input/output buffer coupled to first and second signal transmission paths and configured to receive, from a controller chip communicatively coupled to the non-volatile memory module, a first signal on the first signal transmission path and a second signal on the second signal transmission path;
- and
- means for:
- determining a delay between the first signal and the second signal;
- generating a delay mismatch value based on the determined delay;
- transmitting, to the controller chip, the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer;
- receiving a true signal of a complementary signal pair on the first signal transmission path;
- and
- receiving a complementary signal of the complementary signal pair on the second signal transmission path;
- wherein one of the true signal and the complementary signal is delayed in accordance with the delay mismatch value.
7 more elements
Dependencies are inferred from the claim text.