Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection

A system comprising:

• a receiver communicatively coupled to a transmitter via a communication channel, the receiver comprising:
• a memory having computer readable instructions;
• and
• one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
• monitoring bits received at the receiver via the communication channel for transmission errors, the monitoring comprising:
• receiving frames of bits from the transmitter, the received frames of bits a subset of frames of bits used by the transmitter to generate a multi-frame cyclic-redundancy code (CRC), at least one of the received frames of bits comprising payload bits and a source single check bit not included in the multi-frame CRC, the source single check bit generated by the transmitter based at least in part on bits transmitted by the transmitter to the receiver subsequent to a last CRC check using the multi-frame CRC being performed;
• determining whether a transmission error has occurred in the received frames of bits, the determining comprising:
• generating a calculated single check bit based at least in part on bits in the received frames of bits subsequent to the last CRC check using the multi-frame CRC being performed;
• and
• comparing the received source single check bit to the calculated single check bit, wherein a transmission error has occurred when the received source single check bit does not match the calculated single check bit;
• and
• transmitting an error indication to the transmitter based on determining that a transmission error has occurred, wherein the error indication initiates a change in a CRC rate that is synchronized between the receiver and the transmitter and is performed in parallel with functional operations by the receiver.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:

• monitoring bits received at a receiver via a communication channel for transmission errors, the monitoring comprising:
• receiving frames of bits from a transmitter communicatively coupled to the receiver via the communication channel, the received frames of bits a subset of frames of bits used by the transmitter to generate a multi-frame cyclic-redundancy code (CRC), at least one of the received frames of bits comprising payload bits and a source single check bit not included in the multi-frame CRC, the source single check bit generated by the transmitter based at least in part on bits transmitted by the transmitter to the receiver subsequent to a last CRC check using the multi-frame CRC being performed;
• determining whether a transmission error has occurred in the received frames of bits, the determining comprising:
• generating a calculated single check bit based at least in part on bits in the received frames of bits subsequent to the last CRC check using the multi-frame CRC being performed;
• and
• comparing the received source single check bit to the calculated single check bit, wherein a transmission error has occurred when the received source single check bit does not match the calculated single check bit;
• and
• transmitting an error indication to the transmitter based on determining that a transmission error has occurred, wherein the error indication initiates a recovery sequence that is synchronized between the receiver and the transmitter and is performed in parallel with functional operations by the receiver.