Apparatus for reducing wandering spurs in a fractional-N frequency synthesizer
AssigneeUniversity College Cork, Nui, Cork
InventorsHongjia Mo, Michael Peter Kennedy
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Abstract
The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input a high amplitude dither signal.
Claims12
A fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input the sum of the output of the preceding stage and a high amplitude dither signal,
- wherein the high amplitude dither signal comprises an integer dither signal which is uniformly distributed in the range [0, 1, . . . , M−1], wherein M corresponds to the modulus of the MASH digital delta-sigma modulator.
A fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input the sum of the output of a preceding stage and a high amplitude dither signal,
- wherein the high amplitude dither signal comprises a dither signal which is uniformly distributed in the range [0, 1, . . . , 2K−1]*M/2K, wherein M=2B, and wherein M corresponds to the modulus of the MASH digital delta-sigma modulator, B corresponds to the number of bits, and K comprises an integer between 1 and 6.
A fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input the sum of the output of a preceding stage and a high amplitude dither signal,
- wherein the MASH digital delta-sigma modulator comprises a MASH digital delta-sigma modulator with additive first-order dither,
- wherein the MASH digital delta-sigma modulator comprises a MASH 1-1-1 architecture,
- wherein the MASH 1-1-1 architecture with additive first-order dither comprises a first stage, a second stage and a third stage, and
- wherein the third stage of the MASH architecture is configured to receive as an input the sum of the output of the preceding stage and the high amplitude dither signal.
Dependencies are inferred from the claim text.