US 10,541,703 B2 · Interleaved ADC with estimation of DSA-setting-based IL mismatch

Abstract

An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange). The IL mismatch estimator aggregates, during each aggregation cycle, IL mismatch estimation data based on the selected DSA active data within the DSA allocated subrange, generates an estimate of IL mismatch (IL mismatch estimate) based on the aggregated IL mismatch estimation data, generates IL mismatch correction parameters based on the aggregated IL mismatch estimation data, and generates IL mismatch estimate uncertainty data corresponding to an uncertainty in the IL mismatch estimate used to generate the associated IL mismatch correction parameters for the DSA allocated subrange. A DSA statistics collector to collect a distribution of DSA settings over a pre-defined time period (DSA setting distribution statistics). An estimation subrange allocator coupled to receive DSA setting distribution statistics, and the IL mismatch estimate uncertainty data, and to provide to the estimation subrange blanker the DSA subrange allocation signal according to a pre-defined allocation strategy.

Claims26

Dependent claims

A circuit for analog-to-digital conversion (ADC), comprising:

an RX channel input to receive a RX (receive) signal;
an interleaved ADC (IADC) to convert the RX signal input through the RX channel and an analog signal path, to interleaved (IL) digital data (IADC data stream) for output through a digital signal path;
the RX signal attenuated by a digital step attenuator (DSA) based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a defined number of DSA setting subranges (DSA subranges);
and
an IL mismatch estimation engine in the digital signal path, including:
an estimation subrange blanker coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting (DSA active data) that is within an allocated DSA subrange (DSA allocated subrange);
and
an IL mismatch estimator:
to aggregate, during each aggregation cycle, IL mismatch estimation data (aggregated IL mismatch estimation data) based on the selected DSA active data within the DSA allocated subrange,
to generate an estimate of IL mismatch (IL mismatch estimate) based on the aggregated IL mismatch estimation data, and
to generate IL mismatch correction parameters based on the aggregated IL mismatch estimation data;
a DSA statistics collector to collect a distribution of DSA settings over a pre-defined time period (DSA setting distribution statistics);
and
an estimation subrange allocator to generate the DSA subrange allocation signal for input to the estimation subrange blanker based at least in part on the DSA setting distribution statistics.

11 more elements

A DSA circuit for digital step attenuation (DSA), for use with an interleaved (IL) analog-to-digital converter (IADC) circuit configured to convert a receive (RX) signal input through an RX channel and an analog signal path, to interleaved digital data (IADC data stream) for output through a digital signal path, the DSA circuit comprising:

the RX signal attenuated by the DSA circuit based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a defined number of DSA setting subranges (DSA subranges);
and
an IL mismatch estimation engine in the digital signal path, including:
an estimation subrange blanker coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting (DSA active data) that is within an allocated DSA subrange (DSA allocated subrange);
and
an IL mismatch estimator:
to aggregate, during each aggregation cycle, IL mismatch estimation data (aggregated IL mismatch estimation data) based on the selected DSA active data within the DSA allocated subrange, and
to generate an estimate of IL mismatch (IL mismatch estimate) based on the aggregated IL mismatch estimation data, and
to generate IL mismatch correction parameters based on the aggregated IL mismatch estimation data;
a DSA statistics collector to collect a distribution of DSA settings over a pre-defined time period (DSA setting distribution statistics);
and
an estimation subrange allocator to generate the DSA subrange allocation signal for input to the estimation subrangte blanker based at least in part on the DSA setting distribution statistics.

9 more elements

A method for digital step attenuation (DSA), for use with an interleaved (IL) analog-to-digital converter (IADC) circuit configured to convert a receive (RX) signal input through an RX channel and an analog signal path, to interleaved digital data (IADC data stream) for output through a digital signal path, the method operable to attenuate the RX signal based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a defined number of DSA setting subranges (DSA subranges), the method comprising:

selecting, in response to a DSA subrange allocation signal, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting (DSA active data) that is within an allocated DSA subrange (DSA allocated subrange);
and
performing IL mismatch estimation based on:
aggregating, during each aggregation cycle, IL mismatch estimation data (aggregated IL mismatch estimation data) based on the selected DSA active data within the DSA allocated subrange,
generating generate an estimate of IL mismatch (IL mismatch estimate) based on the aggregated IL mismatch estimation data, and
generating IL mismatch correction parameters based on the aggregated IL mismatch estimation data;
collecting a distribution of DSA settings over a pre-defined time period (DSA setting distribution statistics);
and
generating the DSA subrange allocation signal based at least in part on the DSA setting distribution statistics.

6 more elements

Dependencies are inferred from the claim text.

Interleaved ADC with estimation of DSA-setting-based IL mismatch

Life of this patent

Interleaved ADC with estimation of DSA-setting-based IL mismatch

Life of this patent

Abstract

Claims26