Gain and memory error estimation in a pipeline analog to digital converter
AssigneeTexas Instruments Incorporated
InventorsSrinivas Kumar Reddy Naru, Narasimhan Rajagopal, Shagun Dusad, Viswanathan Nagarajan, Visvesvaraya Appala Pentakota
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Abstract
In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.
Claims20
A stochastic comparator comprising:
- a first comparator configured to compare an input signal and a primary threshold to generate a first signal;
- a second comparator configured to compare the input signal and the primary threshold to generate a second signal;
- a decision block configured to generate a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal;
- and
- a XOR gate configured to generate a detection signal in response the first signal and the second signal.
A pipeline ADC (analog to digital converter) comprising a plurality of stages, and at least one stage comprising:
- a flash ADC configured to receive an input signal and configured to generate a flash output;
- a DAC (digital to analog converter) coupled to the flash ADC and configured to generate a coarse signal in response to the flash output;
- a subtractor coupled to the DAC and configured to generate a residue signal in response to the coarse signal and the input signal;
- and
- a gain amplifier coupled to the subtractor and configured to generate an amplified signal in response to the residue signal, wherein the flash ADC includes one or more stochastic comparators, and each stochastic comparator comprises a first comparator and a second comparator configured to compare the input signal and a primary threshold.
A method comprising:
- comparing an input signal and a primary threshold to generate a first signal;
- comparing the input signal and the primary threshold to generate a second signal;
- generating a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal;
- and
- generating a detection signal by a XOR gate in response to the first signal and the second signal.
A method of gain error estimation in a pipeline ADC, the pipeline ADC comprising a plurality of stages, comprising:
- generating a flash output in response to an input signal by a flash ADC;
- generating a coarse signal in response to the flash output;
- subtracting the coarse signal from the input signal to generate a residue signal;
- and
- amplifying the residue signal to generate an amplified signal, wherein the flash ADC includes one or more stochastic comparators, and each stochastic comparator comprises a first comparator and a second comparator configured to compare the input signal and a primary threshold.
A computing device comprising:
- a processing unit;
- a memory module coupled to the processing unit;
- and
- a logic unit coupled to the processing unit and the memory module, the logic unit comprising a stochastic comparator, the stochastic comparator comprising:
- a first comparator configured to compare an input signal and a primary threshold to generate a first signal;
- a second comparator configured to compare the input signal and the primary threshold to generate a second signal;
- a decision block configured to generate a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal;
- and
- a XOR gate configured to generate a detection signal in response the first signal and the second signal.
Dependencies are inferred from the claim text.