Method and device to align phases of clock signals

A device to align phases of a first clock signal and a second clock signal, the device comprising:

• a phase detector configured to generate a preceding signal and a succeeding signal with respect to the first clock signal to detect a relationship between phases of the first clock signal and the second clock signal;
• a delay generator configured to delay the first clock signal when the second clock signal falls behind the succeeding signal with respect to the first clock signal;
• and
• a controller configured to determine whether the phases of the first clock signal and the second clock signal are aligned with each other according to the relationship detected by the phase detector,
• wherein the first clock signal is generated by passing through a first number of clock buffers, the preceding signal is generated by passing through a second number of clock buffers and the succeeding signal is generated by passing through a third number of clock buffers,
• wherein the second number is less than the first number and the third number is greater than the first number,
• wherein the delay generator includes a plurality of multiplexers connected to each other in sequence, and
• wherein the plurality of multiplexers determines a delay of the first clock signal.