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US 10,541,689 B1Granted
Clock generation circuit and associated circuitry
AssigneeM31 Technology Corporation
InventorsYu Hsiang Chang, Ching-Hsiang Chang
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Abstract
A clock generation circuit arranged in a first system is disclosed. The clock generation circuit includes: a first dual-mode PLL, arranged for generating a first output clock in an integer-N mode or a fractional-N mode selectively, the first output clock being generated based on a first reference clock; and a second dual-mode PLL, arranged for generating a second output clock in an integer-N mode or a fractional-N mode selectively, the second output clock being generated based on the first output clock or a second reference clock selectively. Associated circuitries are also disclosed.
Claims16
A clock generation circuit arranged in a first system, the clock generation circuit comprising:
- a first dual-mode PLL, arranged for generating a first output clock in an integer-N mode or a fractional-N mode selectively, the first output clock being generated based on a first reference clock;
- and
- a 2-to-1 multiplexer, arranged for selecting one of the first output clock and a second reference clock as an output of the 2-to-1 multiplexer according to a first control signal;
- and
- a second dual-mode PLL, arranged for generating a second output clock in an integer-N mode or a fractional-N mode selectively, wherein the second dual-mode PLL operates in the integer-N mode according to a second control signal generated in response to the first control signal when the second reference clock is selected as the output of the 2-to-1 multiplexer.
2 more elements
A circuitry, comprising:
- a clock generation circuit, including:
- a circuit unit, arranged for generating a first control signal, a second control signal and a third control signal;
- a first dual-mode PLL, arranged for generating a first output clock based on a first reference clock, the first dual-mode PLL being configured to operate in an integer-N mode or a fractional-N mode according to the first control signal;
- a 2-to-1 multiplexer, arranged for selectively switching the first output clock or a second reference clock to an output of the 2-to-1 multiplexer according to the second control signal;
- and
- a plurality of second dual-mode PLLs, arranged for generating a plurality of second output clocks respectively based on the output of the 2-to-1 multiplexer, the plurality of second dual-mode PLLs being configured to operate in an integer-N mode or a fractional-N mode, wherein the second dual-mode PLLs operate in the integer-N mode according to the third control signal generated in response to the second control signal when the 2-to-1 multiplexer switches the second reference clock to the output of the 2-to-1 multiplexer.
3 more elements
A circuitry, comprising:
- a clock generation circuit, including:
- a single-mode PLL, arranged for generating a first output clock based on a first reference clock in an integer-N mode;
- a 2-to-1 multiplexer, arranged for selectively switching the first output clock or a second reference clock to an output of the 2-to-1 multiplexer according to a first control signal;
- and
- a plurality of dual-mode PLLs, arranged for generating a plurality of second output clocks respectively based on the output of the 2-to-1 multiplexer, the dual-mode PLLs being configured to operate in an integer-N mode or a fractional-N mode selectively, wherein the dual-mode PLLs operate in the integer-N mode according to a second control signal generated in response to the first control signal when the 2-to-1 multiplexer switches the second reference clock to the output of the 2-to-1 multiplexer.
2 more elements
A circuitry, comprising:
- a clock generation circuit, including:
- a single-mode PLL, arranged for generating a first output clock based on a first reference clock in an integer-N mode;
- a 2-to-1 multiplexer, arranged for selectively switching the first output clock or a second reference clock to an output of the 2-to-1 multiplexer according to a first control signal;
- and
- a dual-mode PLL, arranged for generating a second output clock based on the output of the 2-to-1 multiplexer, the dual-mode PLL being configured to operate in an integer-N mode or a fractional-N mode selectively, wherein the dual-mode PLL operates in the integer-N mode according to a second control signal generated in response to the first control signal when the 2-to-1 multiplexer switches the second reference clock to the output of the 2-to-1 multiplexer.
2 more elements
Dependencies are inferred from the claim text.