Multiplexing latch circuit and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHyunsung Hong
Life of this patent
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Abstract
A circuit includes a clock generator configured to generate a first latching clock signal and a second latching clock signal. Responsive to a select signal, one of the first latching clock signal or the second latching clock signal has a clock signal frequency and the other of the first latching clock signal or the second latching clock signal has a predetermined logic value. A multiplexing latch circuit is configured to select either first data on a first data line or second data on a second data line based on the first latching clock signal and the second latching clock signal.
Claims20
A circuit, comprising:
- a clock generator configured to generate a first latching clock signal and a second latching clock signal, wherein, responsive to a select signal, one of the first latching clock signal or the second latching clock signal has a clock signal frequency and the other of the first latching clock signal or the second latching clock signal has a predetermined logic value;
- and
- a multiplexing latch circuit configured to select either first data on a first data line or second data on a second data line based on the first latching clock signal and the second latching clock signal.
A circuit, comprising:
- a clock generator configured to, responsive to a select signal, generate a first latching clock signal having one of a clock signal frequency or a predetermined logic value, and generate a second latching clock signal having the other of the clock signal frequency or the predetermined logic value;
- and
- a multiplexing latch circuit comprising:
- a first selecting circuit configured to receive the first latching clock signal;
- and
- a second selecting circuit configured to receive the second latching clock signal,
- wherein each of the first selecting circuit and the second selecting circuit is configured to select data on a data line responsive to the corresponding latching clock signal having the clock signal frequency.
A method of selecting data in a circuit, the method comprising:
- in response to a select signal, generating a first latching clock signal having a clock signal frequency;
- in response to the select signal, generating a second latching clock signal having a predetermined logic value;
- and
- in response to the first latching clock signal and the second latching clock signal, selecting either a first data on a first data line or a second data on a second data line using a latching device.
Dependencies are inferred from the claim text.