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US 10,541,680 B2Granted
Low area enable flip-flop
AssigneeTexas Instruments Incorporated
InventorsSubhankar Das, Soman Purushothaman
Life of this patent
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Abstract
The disclosure provides a flip-flop. The flip-flop includes a master latch. The master latch receives a flip-flop input, a clock input, an inverted clock input, an enable signal and an inverted enable signal. A slave latch is coupled to the master latch and receives the enable signal and the inverted enable signal. An output inverter is coupled to the slave latch and generates a flip-flop output.
Claims7
A flip-flop comprising:
- multiplexer circuitry having a data input and a scan data input, the multiplexer circuitry having a scan input and an inverted scan input as selection signals, the multiplexer circuitry having a multiplexer output;
- control circuitry having an input coupled to the inverted scan input, an inverted enable input, a control output, and an inverted control output;
- a master latch having an input coupled to the multiplexer output, a clock input, an inverted clock input, a control input coupled to the control output, an inverted control input couple to the inverted control output, and a master latch output;
- a slave latch having a slave latch input coupled to the master latch output, an input coupled to the control output, an input coupled to the inverted control output, and having a slave latch output;
- and
- an output inverter having a data input coupled to the slave latch output having a flip-flop output.
3 more elements
Dependencies are inferred from the claim text.