US 10,541,525 B1 · Configurable retry for system operations

Abstract

The present disclosure relates to configuring parameters of a system. In some examples, a timer duration circuit can be configured to output a timer duration signal defining a time duration for a retry signal based on an impedance of a first circuit coupled at a first node. A logic circuit can be configured to control an output of the retry signal to at least one integrator circuit to control a current to a second node based on one of the timer duration signal and a retry timer signal, and a combination thereof. An output circuit can be configured to output a stop retry signal based on a voltage established by a second circuit at the second node based on its impedance and the current. The stop retry signal can indicate a number of retries that have occurred and can be based on the capacitances of the first and second circuits.

Claims20

Dependent claims

A system comprising:

a timer duration circuit coupled to a first node and configured to output a timer duration signal, wherein a first circuit is coupled to the first node, and the timer duration signal defines a time duration for a retry signal based on an impedance of the first circuit;
a logic circuit configured to control the retry signal that is output to at least one integrator circuit to control a current to a second node based on one of the timer duration signal, a retry timer signal (RTRS), and a combination thereof, wherein a second circuit is coupled to the second node and to provide a voltage at the second node based on an impedance of the second circuit and the current;
and
an output circuit configured to output a stop retry signal based on the voltage at the second node, wherein the stop retry signal is to indicate a number of retries that have occurred, the number of retries being set based on the impedances of the first and second circuits.

1 more element

A system comprising:

a first circuit configured to receive output signals from flip-flop circuits of a counter established based on a voltage at a node of an auto retry system in response to a retry timer signal (RTRS) over time intervals, wherein the first circuit is configured to provide a counter count signal based on the output signals, wherein the counter count signal is to indicate a shifted number of retries of an actual number of retries stored at the counter that have occurred over the time intervals;
and
a second circuit configured to output a stop retry signal based on the counter count signal and a decoded retry signal outputted following a given number of pulses of the RTRS over the time intervals, wherein the stop retry signal indicates that a given number of retries have occurred.

Dependencies are inferred from the claim text.

Configurable retry for system operations

Life of this patent

Configurable retry for system operations

Life of this patent

Abstract

Claims20