Display device and electronic device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsHideaki Shishido, Naoto Kusumoto
Life of this patent
Estimating the term…
Abstract
A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit.
Claims13
A display device comprising a pixel circuit and a driver circuit provided on a same plane,
- wherein the driver circuit includes a selection circuit and a buffer circuit,
- wherein the selection circuit includes a first transistor,
- wherein the buffer circuit includes a second transistor,
- wherein the first transistor includes a region overlapping with the second transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,
- wherein one of a source and a drain of the second transistor is electrically connected to the pixel circuit, and
- wherein transistors included in the driver circuit and the pixel circuit have a same conductivity.
A display device comprising a pixel circuit and a driver circuit provided on a same plane,
- wherein the driver circuit includes a selection circuit and a buffer circuit,
- wherein the selection circuit includes a first transistor,
- wherein the buffer circuit includes a second transistor,
- wherein the pixel circuit includes a third transistor and a fourth transistor,
- wherein the first transistor includes a region overlapping with the second transistor,
- wherein the third transistor includes a region overlapping with the fourth transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, and
- wherein one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor.
Dependencies are inferred from the claim text.