Edge termination designs for silicon carbide super-junction power devices

A silicon carbide (SiC) super-junction (SJ) device, comprising:

• a first SiC semiconductor layer of a first conductivity-type, wherein the first SiC semiconductor layer comprises a first plurality of implanted regions of a second conductivity-type that form an active region and a termination region of the first SiC semiconductor layer, and a first plurality of spacings respectively disposed between the first plurality of implanted regions, wherein the termination region of the first SiC semiconductor layer has a first effective doping profile;
• and
• at least one second SiC semiconductor layer of the first conductivity-type disposed below the first SiC semiconductor layer and closer to a substrate layer than the first semiconductor layer, wherein the at least one second SiC semiconductor layer includes a second plurality of implanted regions of the second conductivity-type that form a second active region and a second termination region of the at least one second SiC semiconductor layer, and a second plurality of spacings respectively disposed between the second plurality of implanted regions, wherein the second termination region of the at least one second SiC semiconductor layer has a second effective doping profile that is different from the first effective doping profile;
• and
• wherein the first plurality of implanted regions of the first SiC semiconductor layer and the second plurality of implanted regions of the second SiC semiconductor layer include an equal number of implanted regions,
• wherein each of the first plurality of implanted regions of the first SiC semiconductor layer has a respective width that is substantially equal to, and is substantially aligned with, a respective width of a corresponding implanted region of the second plurality of implanted regions of the second SiC semiconductor layer, and
• wherein each of the first plurality of spacings of the first SiC semiconductor layer has a respective spacing width that is substantially equal to, and is substantially aligned with, a respective spacing width of a corresponding spacing of the second plurality of spacings of the second SiC semiconductor layer.

A method of manufacturing a silicon carbide (SiC) super-junction (SJ) device, comprising:

• fabricating a lower SiC semiconductor layer of the SiC-SJ device, comprising:
• forming the lower SiC semiconductor layer having a first conductivity-type on top of a SiC substrate layer;
• fabricating an active region in the lower SiC semiconductor layer by forming a first plurality of implanted regions having a second conductivity-type in a portion of the lower SiC semiconductor layer;
• and
• fabricating a termination region in the lower SiC semiconductor layer by forming a second plurality of implanted regions having the second conductivity-type in another portion of the lower SiC semiconductor layer adjacent the active region according to a first effective doping profile, wherein the termination region in the lower SiC semiconductor layer comprises a first plurality of spacings respectively disposed between the second plurality of implanted regions;
• and
• fabricating a top SiC semiconductor layer of the SiC-SJ device, comprising:
• forming the top SiC semiconductor layer having the first conductivity-type above the lower SiC semiconductor layer;
• fabricating an active region in the top SiC semiconductor layer by forming a third plurality of implanted regions having the second conductivity-type in a portion of the top SiC semiconductor layer;
• and
• fabricating a termination region in the top SiC semiconductor layer by forming a fourth plurality of implanted regions having the second conductivity-type in another portion of the top SiC semiconductor layer adjacent the active region according to a second effective doping profile, wherein the first effective doping profile is different from the second effective doping profile, wherein the termination region in the top SiC semiconductor layer comprises a second plurality of spacing respectively disposed between the fourth plurality of implanted regions;
• and
• wherein the second plurality of implanted regions in the lower SiC semiconductor layer and the fourth plurality of implanted regions in the top SiC semiconductor layer include an equal number of implanted regions,
• wherein each of the second plurality of implanted regions in the lower SiC semiconductor layer has a respective width that is substantially equal to, and is substantially aligned with, a respective width of a corresponding implanted region of the fourth plurality of implanted regions in the top SiC semiconductor layer, and
• wherein each of the first plurality of spacings of the lower SiC semiconductor layer has a respective spacing width that is substantially equal to, and is substantially aligned with, a respective spacing width of a corresponding spacing of the second plurality of spacings of the top SiC semiconductor layer.