US 10,541,334 B2 · Techniques for integration of Ge-rich p-MOS source/drain

Abstract

Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

Claims20

Dependent claims

An integrated circuit, comprising:

a non-planar body comprising semiconductor material, wherein the non-planar body has top and side surfaces;
a gate structure on at least the top and side surfaces of the non-planar body;
a source region adjacent the non-planar body, the source region including a first portion, the first portion including germanium at a concentration of at least 50 atomic percent throughout the first portion, wherein the first portion is in direct contact with a surface that consists essentially of silicon;
and
a drain region adjacent the non-planar body, the drain region including a second portion, the second portion including germanium at a concentration of at least 50 atomic percent throughout the second portion, wherein the second portion is in direct contact with the surface that consists essentially of silicon.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/199,445Filed 26 Nov 2018 · continuation

Priority

2 Jan 2018

Published

US 2019/0109234 A111 Apr 2019

Granted

21 Jan 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification34 codes

H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
B82Y 10/00
Nanotechnology for information processing, storage or transmission
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/0275
Of lateral single-gate IGFETs: forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised…

Family

PCT/US2014/031486Parent of this continuation · filed 21 Mar 2014

Application15/860,292Parent of this continuation · filed 2 Jan 2018

US 9,859,424 B2Parent of this continuation · filed 2 Jan 2018

US 2019/0109234 A1Pre-grant publication · published 11 Apr 2019

US 10,147,817 B2Parent of this continuation

Application15/116,453Parent of this continuation

US 2017/0012124 A1Published application

US 2018/0145174 A1Published application

US 10,541,334 B2This patent

From the US filing history. Foreign family members aren’t listed.

Techniques for integration of Ge-rich p-MOS source/drain

Life of this patent

Techniques for integration of Ge-rich p-MOS source/drain

Life of this patent

Abstract

Claims20