Method of forming a metal gate using monolayers
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJu-Li Huang, Chun-Sheng Liang, Ming-Chi Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Hsin-Che Chiang
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Abstract
Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.
Claims20
A method for semiconductor processing, the method comprising:
- forming a first capping layer over a gate dielectric layer disposed on a fin of a substrate, a gate spacer being disposed over the fin laterally abutting the gate dielectric layer;
- forming a second capping layer over the first capping layer;
- removing the second capping layer using a wet etching solution, wherein the wet etching solution includes a borate ligand-containing species, wherein removing the second capping layer forms a first monolayer;
- forming metal layer over the first monolayer;
- forming a second monolayer over a portion of the metal layer;
- and
- removing a portion of the metal layer using the second monolayer as a mask.
A method for semiconductor processing, the method comprising:
- forming a metal layer over a gate dielectric layer disposed on a substrate;
- forming a hardmask monolayer comprising phosphorous over a first portion of the metal layer by exposing the first portion of the metal layer to a wet solution including a phosphorous-containing species;
- and
- removing a second portion of the metal layer, wherein the hardmask monolayer prevents removal of the first portion of the metal layer during removal of the second portion of the metal layer.
A method for semiconductor processing, the method comprising:
- forming a first capping layer over a gate dielectric layer disposed on a fin of a substrate, a gate spacer being disposed over the fin laterally abutting the gate dielectric layer;
- forming a second capping layer over the first capping layer;
- removing the second capping layer using a wet etching solution, wherein removing the second capping layer forms a first self-assembled monolayer (SAM) over the first capping layer;
- forming a barrier layer over the first SAM;
- forming a mask layer over the barrier layer in a first region;
- forming a second SAM over the barrier layer in a second region;
- removing the mask layer;
- and
- etching the barrier layer using the second SAM as a mask.
Dependencies are inferred from the claim text.