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US 10,541,315 B2Granted
INP-based transistor fabrication
AssigneePurdue Research Foundation
InventorsPeide Ye, Zhiyuan Cheng, Yi Xuan, Yanqing Wu, Bunmi Adekore, James Fiorenza
Life of this patent
Estimating the term…
Abstract
Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.
Claims20
A method comprising:
- forming a mask layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant, the mask layer comprising a non-crystalline dielectric material;
- patterning the mask layer to form an opening in the mask layer, the opening exposing a portion of the substrate;
- forming a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, a topmost surface of the buffer layer being below a topmost surface of the mask layer, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening;
- forming a semiconductor layer over the buffer layer in the opening, the semiconductor layer fully filling the opening, the semiconductor layer being made of a single third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant;
- and
- forming a gate stack over the semiconductor layer, wherein the topmost surface of the mask layer is level with a topmost surface of the semiconductor layer after forming the gate stack.
3 more elements
A method comprising:
- forming a non-crystalline dielectric layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant;
- etching the non-crystalline dielectric layer to form an opening in the non-crystalline dielectric layer, the opening exposing a portion of the substrate, the opening having a first width and a first height;
- epitaxially growing a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, the buffer layer having a second height less than the first height, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening below a third height, the third height being less than the second height, the third height being between one half of the first width and two times the first width;
- epitaxially growing a semiconductor layer over the buffer layer in the opening, a topmost surface of the semiconductor layer being level with a topmost surface of the non-crystalline dielectric layer, the semiconductor layer being made of a single third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant;
- forming a gate dielectric over the semiconductor layer;
- and
- forming a gate electrode over the gate dielectric, wherein a topmost surface of the buffer layer is below with the topmost surface of the non-crystalline dielectric layer after forming the gate electrode.
4 more elements
A method comprising:
- forming a non-crystalline dielectric layer over a crystalline Si layer;
- etching the non-crystalline dielectric layer to form an opening in the non-crystalline dielectric layer, the opening exposing a topmost surface of the crystalline Si layer, the opening having a first width and a first height;
- epitaxially growing a buffer layer in the opening, the buffer layer comprising a crystalline semiconductor material having a lattice constant different from a lattice constant of crystalline Si, the buffer layer having a second height less than the first height, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening below a third height, the third height being less than the second height, the third height being between one half of the first width and two times the first width;
- epitaxially growing a crystalline InP layer over and in physical contact with the buffer layer in the opening, a topmost surface of the crystalline InP layer being level with a topmost surface of the non-crystalline dielectric layer, the lattice constant of the buffer layer being substantially same as a lattice constant of crystalline InP;
- and
- forming a gate stack over and in physical contact with the topmost surface of the crystalline InP layer, wherein the topmost surface of the crystalline InP layer remains level with the topmost surface of the non-crystalline dielectric layer after forming a gate stack.
3 more elements
Dependencies are inferred from the claim text.