High Electron Mobility Transistor with dual thickness barrier layer

A method of forming a semiconductor device, the method comprising:

• providing a heterojunction semiconductor body, the heterojunction semiconductor body comprising a first type III-V semiconductor layer and a second type III-V semiconductor layer formed over the first type III-V semiconductor layer, the second type III-V semiconductor layer having a different bandgap as the first type III-V semiconductor layer such that a first two-dimensional charge carrier gas forms at an interface between the first and second type III-V semiconductor layers,
• wherein the heterojunction semiconductor body is provided such that the second type III-V semiconductor layer comprises a thicker section and a thinner section,
• forming a first input-output electrode on the thicker section of the second type III-V semiconductor layer, the first input-output electrode being in ohmic contact with the first two-dimensional charge carrier gas;
• forming a second input-output electrode on the thinner section of the second type III-V semiconductor layer, the second input-output electrode being in ohmic contact with the first two-dimensional charge carrier gas;
• and
• forming a gate structure on the thinner section of the second type III-V semiconductor layer, the gate structure being configured to control a conductive connection between the first and second input-output electrodes,
• wherein the gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer,
• wherein the thinner section of the second type III-V semiconductor layer comprises a first planar upper surface that extends along a single plane and reaches the transition, the first planar upper surface being opposite from a lower surface of the second type III-V semiconductor layer that faces the first type III-V semiconductor layer, and wherein the gate structure and the second input-output electrode are formed on the first planar upper surface,
• wherein forming the gate structure comprises:
• forming a first doped type III-V semiconductor region on the first planar upper surface;
• and
• forming an electrically conductive gate electrode on the first doped type III-V semiconductor region, and
• wherein a complete lower side of the first doped type III-V semiconductor region faces and is coplanar with the first planar upper surface, and wherein material properties of the first doped III-V semiconductor region locally deplete the first two-dimensional charge carrier gas in the absence of external bias such that the semiconductor device is normally-off.