Integrated circuit device and method of manufacturing the same

An integrated circuit device comprising:

• a substrate comprising a cell array region including a cell active region and a peripheral circuit region including a peripheral circuit active region separated from each other along a direction parallel to an upper surface of the substrate;
• a first device isolation layer filling an interface trench extending in an interface region between the cell array region and the peripheral circuit region and defining a portion of the cell active region and a portion of the peripheral circuit active region;
• an insulation pattern extending from the cell array region to an upper portion of the first device isolation layer, wherein the insulation pattern covers an upper surface of the cell active region and at least a portion of the first device isolation layer, and wherein the insulation pattern defines an undercut area on an upper surface of the first device isolation layer;
• and
• a buried pattern substantially filling the undercut region,
• wherein the buried pattern comprises a seam line extending from a surface of the buried pattern toward an inner portion of the buried pattern, and an air gap formed at an end of the seam line.

An integrated circuit device comprising:

• a substrate comprising a cell array region including a cell active region and a peripheral circuit region including a peripheral circuit active region separated from each other along a direction parallel to an upper surface of the substrate;
• a first device isolation layer filling an interface trench extending in an interface region between the cell array region and the peripheral circuit region and defining a portion of the cell active region and a portion of the peripheral circuit active region;
• an insulation pattern extending from the cell array region to an upper portion of the first device isolation layer, wherein the insulation pattern covers an upper surface of the cell active region and at least a portion of the first device isolation layer, and wherein the insulation pattern defines an undercut area on an upper surface of the first device isolation layer;
• and
• a buried pattern substantially filling the undercut region,
• wherein the first device isolation layer comprises a first insulation liner, a second insulation liner, and a buried insulating layer that are sequentially stacked on an inner wall of the interface trench, and wherein the buried pattern is in direct contact with the buried insulating layer.