Memory arrays, and methods of forming memory arrays

A NAND memory array, comprising:

• a vertical stack of alternating first and second levels;
• the first levels comprising first material, and the second levels comprising a conductive core material and a conductive liner material lining the conductive core material and having terminal ends along an opening extending through the first and second levels, the terminal ends corresponding to control gate regions;
• the first and second levels all having sidewall surfaces along the opening;
• segments of charge-trapping material along the sidewall surfaces of the second levels, the charge-trapping material being entirely within the opening;
• charge-tunneling material extending along the first and second levels, and spaced from the second levels by the charge-trapping material, the segments of charge-trapping material having upper surfaces and lower in direct physical contact with the charge-tunneling material;
• and
• channel material within the opening extending along the charge-tunneling material.

A vertical NAND memory string comprising:

• a plurality of conductive levels with each individual conductive level comprised by the plurality of conductive levels being spaced from each adjacent conductive level by an intervening insulative level;
• each of the conductive levels and each of the intervening insulative levels having a terminal end along an opening;
• segments of charge-blocking material along the terminal ends of the conductive levels;
• segments of charge-trapping material along the terminal ends of the conductive levels and spaced from the terminal ends of the conductive levels by the charge-blocking material, the segments of charge-trapping material being vertically spaced from one another by a gap along the terminal end of the corresponding intervening insulative level;
• and
• segments of charge-trapping material within the gap and in direct physical contact with upper and lower surfaces of the segments of charge-trapping material.