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AssigneeSamsung Electronics Co., Ltd.
InventorsSang-Hoon Baek, Sun-Young Park, Sang-Kyu Oh, Ha-Young Kim, Jung-Ho Do, Moo-Gyu Bae, Seung-Young Lee
Estimating the term…
A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.
A method of forming a system on chip (SoC), the method comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Of only field-effect components: of only insulated-gate FETs [IGFET]
Static random access memory [SRAM] devices: comprising a MOSFET load element
The components including insulated gates, e.g. IGFETs: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
The components including insulated gates, e.g. IGFETs: the components including FinFETs
About 8 years 11 months of term left · ends 1 Oct 2035 (estimated)
Exemplary embodiments relate to a system on chip (SoC), more particularly, to and SOC comprising a gate contact structure.
Multigate transistors have been suggested as one of the scaling technologies to increase density of a semiconductor device, in which a multichannel active pattern (or silicon body) in a fin or nanowire form is formed on a substrate, and then gates are formed on a multichannel active pattern surface.
Because the multigate transistor uses a three-dimensional channel, scaling is facilitated. Further, electric current control ability can be enhanced without having to increase lengths of the gates of the multigate transistor. Furthermore, it is possible to effectively control short channel effect (SCE) in which electric potential in channel region is influenced by the drain voltage.
FIG. 1 is a block diagram and FIG. 2 is a circuit diagram, each illustrating a non-volatile memory device comprising a semiconductor device according to exemplary embodiments;
FIG. 3 is a layout provided to explain a semiconductor device according to an exemplary embodiment;
FIG. 4 is a cross section taken on line A1-A2 of FIG. 3;
Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings. The exemplary embodiments may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. The same reference numbers indicate the same components throughout the specification. In the attached figures, the thickness of layers and regions is exaggerated for clarity.
It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.