Semiconductor device

A semiconductor device comprising:

• a semiconductor chip including a first front surface, a first back surface on the opposite side to the first front surface, and, in the first front surface, a plurality of electrodes arranged in a plurality of rows from the outermost periphery closest to the outer edge of the first front surface toward the center of the first front surface;
• and
• a wiring substrate including a first main surface over which the semiconductor chip is mounted, a second main surface on the opposite side to the first main surface, and a plurality of wiring layers located between the first main surface and the second main surface,
• wherein the electrodes of the semiconductor chip include a plurality of first signal electrodes for transmitting a first signal as one of an input signal and an output signal, a plurality of second signal electrodes for transmitting a second signal as the other of an input signal and an output signal, a plurality of first potential electrodes supplied with first potential, and a plurality of second potential electrodes supplied with second potential different from the first potential,
• wherein in the first front surface of the semiconductor chip,
• the first signal electrodes are arranged in a first row between the outer edge of the first front surface and the center of the first front surface,
• the first potential electrodes and the second potential electrodes are arranged in a second row between the first row and the center of the first front surface, and
• the second signal electrodes are arranged in a third row between the second row and the center of the first front surface,
• wherein the wiring layers of the wiring substrate include a first wiring layer located between the first main surface and the second main surface, a second wiring layer located between the first wiring layer and the second main surface, a third wiring layer located between the second wiring layer and the second main surface, a fourth wiring layer located between the third wiring layer and the second main surface, and a fifth wiring layer located between the fourth wiring layer and the second main surface,
• wherein the wiring substrate includes:
• a plurality of first signal wirings formed in the second wiring layer and respectively coupled to the first signal electrodes;
• a plurality of second signal wirings formed in the fourth wiring layer and respectively coupled to the second signal electrodes;
• a first conductor pattern formed in the first wiring layer and supplied with the second potential;
• a second conductor pattern formed in the second wiring layer and electrically coupled with the first conductor pattern;
• a third conductor pattern formed in the third wiring layer and electrically coupled with the second conductor pattern;
• a fourth conductor pattern formed in the fourth wiring layer and electrically coupled with the third conductor pattern;
• and
• a fifth conductor pattern formed in the fifth wiring layer and electrically coupled with the fourth conductor pattern,
• wherein as viewed in a plane, a part of each of the first signal wirings overlaps with a part of each of the second signal wirings, and
• wherein as viewed in a plane, each of the first conductor pattern, the third conductor pattern, and the fifth conductor pattern overlaps with the second conductor pattern, the fourth conductor pattern, the first signal wirings, and the second signal wirings.