Control warpage in a semiconductor chip package
AssigneeInternational Business Machines Corporation
InventorsTuhin Sinha, Krishna R. Tunga
Life of this patent
Estimating the term…
Abstract
A method to control warpage in a semiconductor chip package that includes: attaching a semiconductor chip to a semiconductor chip package; attaching a stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, the stiffener having a coefficient of thermal expansion (CTE) less than that of the substrate on which the chip is assembled; attaching the semiconductor chip package to a laminate substrate; and removing the stiffener.
Claims20
A method to control warpage in a semiconductor chip package comprising:
- attaching a semiconductor chip to a semiconductor chip package, the semiconductor chip package having at least signal distribution and power distribution functions;
- underfilling the semiconductor chip with an underfill material;
- attaching a stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, the stiffener having a coefficient of thermal expansion (CTE) less than that of the semiconductor chip package;
- attaching the semiconductor chip package to a laminate substrate wherein the laminate substrate comprises a material selected from the group consisting of BT-epoxy, FR4, polyimide and central glass reinforced epoxy core with polymer build-up resin layers on either side of the core;
- underfilling the semiconductor chip package with an underfill material;
- and
- removing the stiffener after attaching the semiconductor chip package to the laminate substrate.
A method to control warpage in a semiconductor chip package comprising:
- attaching a semiconductor chip to a semiconductor chip package, the semiconductor chip package having at least signal distribution and power distribution functions;
- attaching a stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, the stiffener having a coefficient of thermal expansion (CTE) less than that of the semiconductor chip package;
- attaching the semiconductor chip package to a laminate substrate wherein the laminate substrate comprises a material selected from the group consisting of BT-epoxy, FR4, polyimide and central glass reinforced epoxy core with polymer build-up resin layers on either side of the core;
- and
- removing the stiffener after attaching the semiconductor chip package to the laminate substrate.
A method to control warpage in a semiconductor chip package comprising:
- attaching by a solder ball connection a semiconductor chip to a semiconductor chip package, the semiconductor chip package having at least signal distribution and power distribution functions;
- underfilling the semiconductor chip with an underfill material;
- adhesively attaching an optically transparent stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, wherein the stiffener is in the form of a frame that surrounds the semiconductor chip, the stiffener having a coefficient of thermal expansion (CTE) less than that of the semiconductor chip package;
- attaching by a solder ball connection the semiconductor chip package to a laminate substrate wherein the laminate substrate comprises a material selected from the group consisting of BT-epoxy, FR4, polyimide and central glass reinforced epoxy core with polymer build-up resin layers on either side of the core;
- underfilling the semiconductor chip package with an underfill material;
- and
- removing the stiffener by a laser ablation process after attaching the semiconductor chip package to the laminate substrate.
Dependencies are inferred from the claim text.