Semiconductor package, package-on-package device, and method of fabricating the same

A semiconductor package comprising:

• a package substrate;
• a semiconductor chip on a first surface of the package substrate;
• a connection substrate on the package substrate, the connection substrate spaced apart from and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough;
• a plurality of first connecting elements between the semiconductor chip and the package substrate, the plurality of first connecting elements electrically connecting the semiconductor chip to the package substrate;
• a plurality of second connecting elements between the connection substrate and the package substrate, the plurality of second connecting elements electrically connecting the connection substrate to package substrate;
• a mold layer encapsulating the semiconductor chip and the connection substrate;
• and
• an upper redistribution pattern on the mold layer and the semiconductor chip, the upper redistribution pattern electrically connected to a corresponding one of the plurality of conductive connection structures.

A semiconductor package comprising:

• a first semiconductor unit package including,
• a first package substrate,
• a first semiconductor chip on a first surface of the first package substrate,
• a connection substrate on the first package substrate, the connection substrate spaced apart from and surrounding the first semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough,
• a plurality of first connecting elements between the first semiconductor chip and the first package substrate, the plurality of first connecting elements electrically connecting the first semiconductor chip to the first package substrate,
• a plurality of second connecting elements between the connection substrate and the first package substrate, the plurality of second connecting elements electrically connecting the connection substrate to the first package substrate,
• a mold layer encapsulating the first semiconductor chip and the connection substrate, and
• an upper redistribution pattern on the mold layer and the first semiconductor chip, the upper redistribution pattern electrically connected to a corresponding one of the a plurality of conductive connection structures;
• and
• a second semiconductor unit package electrically connected to the upper redistribution pattern of the first semiconductor unit package, the second semiconductor unit package including,
• a second package substrate, and
• a second semiconductor chip on a first surface of the second package substrate.