Chip package and chip packaging method
AssigneeChina Wafer Level CSP Co., Ltd.
InventorsZhiqi Wang, Guoliang Xie, Hanqing Hu
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Abstract
A chip package and a chip packaging method are provided. The package includes: a chip to be packaged, a reinforcing layer and solder bumps. The chip to be packaged includes a first surface and a second surface opposite to each other, the first surface includes a sensing region and first contact pads, and the first contact pads are electrically coupled to the sensing region. The reinforcing layer covers the first surface of the chip to be packaged. The solder bumps are provided on the second surface of the chip to be packaged. The solder bump is electrically connected to the first contact pad and is configured to electrically connect with an external circuit.
Claims13
A chip package, comprising:
- a chip to be packaged, wherein the chip to be packaged comprises a first surface and a second surface opposite to each other, the first surface comprises a sensing region and first contact pads, and the first contact pads are electrically coupled to the sensing region;
- a reinforcing layer covering the first surface of the chip to be packaged;
- and
- solder bumps provided on the second surface of the chip to be packaged, wherein the solder bump is electrically connected to the first contact pad and is configured to electrically connect with an external circuit,
- wherein a thickness of the reinforcing layer ranges from 2 μm to 40 μm, inclusive.
Dependencies are inferred from the claim text.