Apparatus and method for wafer thinning in advanced packaging applications
AssigneeVeeco Precision Surface Processing LLC
InventorsLaura Mauer, John Taddei, John Clark, Kenji Nulman
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Abstract
A system and method are provided for etching semiconductor wafers (integrated circuit substrates) with advanced packaging using a two-step wet etching process. The first etch step uses an etchant that is non-selective to at least the wafer material (silicon) and metals, such as copper and titanium, that are present in the wafer. The second etch step uses an etchant that is selective to the wafer material (silicon) and has low selectivity for the metals, thereby leaving them at least substantially intact.
Claims31
A method for wet-etching a wafer having a fan-out wafer level packaging (FOWLP) construction with one or more interconnect pads located within a redistribution layer (RDL) beneath a surface of wafer material to produce a processed wafer with each of the interconnect pads being exposed, the method comprising the steps of:
- measuring, at a measurement station, an initial thickness of the wafer;
- etching the surface of the wafer according to a first etch recipe and using a first etchant to thin the wafer material and leave a layer of residual wafer material having a prescribed residual substrate material thickness (RST) above the one or more interconnect pads, wherein the first etch recipe is based on the measured initial thickness of the wafer;
- etching the surface of the wafer according to a second etch recipe using a second etchant to thin the wafer material such that a respective portion of each of the interconnect pads is exposed;
- and
- wherein the first and second etchants comprise different chemical compositions;
- wherein the first etchant comprises an isotropic etchant and the second etchant comprises an anisotropic etchant.
A method for wet-etching a wafer having a fan-out wafer level packaging (FOWLP) construction with at least one metal interconnect pad located within a redistribution layer (RDL) beneath a surface of the wafer to produce a processed wafer with the at least one metal interconnect pad being at least partially exposed the method comprising the steps of:
- measuring, at a measurement station, an initial thickness of the wafer at each of a plurality of radial locations along the wafer;
- calculating, by a process controller, a respective first etch depth for each of the plurality of radial locations, wherein the respective first etch depth for a particular radial location is the amount of material to be removed at the particular radial location during the first etching step and is a function of the measured initial thickness of the particular radial location and a prescribed respective residual substrate material thickness (RST) which is a thickness of a layer of residual wafer material left over the at least one interconnect pad after the first etching step, and wherein the respective first etch depths are non-uniform;
- generating, with the process controller, a first-etch recipe based on the calculated respective first etch depths, wherein the first etch recipe controls movement of a nozzle during the first etching step causing the nozzle to selectively dispense a first etchant onto each of the plurality radial locations thereby thinning the wafer at each radial location the respective first etch depths, wherein the first etch depths are depths that do not reveal the at least one interconnect pad;
- etching, at a first etching station, the surface of the wafer according to the first etch recipe and using the first etchant;
- etching, at a second etching station, the surface of the wafer according to a second etch recipe using a second etchant to thin the wafer material such that a respective portion of the at least one interconnect pad is exposed;
- and
- wherein the first etching step is an isotropic wet-etching step, the second etching step is an anisotropic wet-etching step, and the first and second etchants comprise different chemical compositions.
Dependencies are inferred from the claim text.