Vertical silicon/silicon-germanium transistors with multiple threshold voltages

A method of forming vertical fin field effect transistors with different threshold voltages, comprising:

• forming a silicon-germanium cap layer on a substrate, wherein the silicon-germanium cap layer has a germanium concentration in the range of about 20 at. % to about 30 at. %;
• forming a vertical fin with a silicon-germanium cap from the silicon-germanium cap layer and the substrate;
• and
• forming a silicon-germanium doping layer directly on the exposed surfaces of the substrate, the vertical fin, and the silicon-germanium cap.

A method of forming vertical fin field effect transistors, comprising:

• forming a silicon-germanium cap layer on a substrate;
• forming a vertical fin with a silicon-germanium cap from the silicon-germanium cap layer and the substrate;
• forming a silicon-germanium doping layer directly on the exposed surfaces of the substrate, vertical fin, and silicon-germanium cap;
• and
• forming a protective liner on the silicon-germanium doping layer and silicon-germanium cap.