US 10,541,128 B2 · Method for making VFET devices with ILD protection

Abstract

A method of forming a semiconductor device and resulting structures having an etch-resistant interlayer dielectric (ILD) that maintains height during a top epitaxy clean by forming a dielectric layer on a semiconductor structure; wherein the dielectric layer includes a first dielectric material; converting at least a portion of the dielectric layer to a second dielectric material; and exposing the portion of the dielectric layer to an etch material; wherein the etch material includes a first etch characteristic defining a first rate at which the etch material etches the first dielectric material; and wherein the etch material further includes a second etch characteristic defining a second rate at which the etch material etches the portion of the dielectric layer; wherein the first rate is different than the second rate.

Claims13

Dependent claims

A method for forming a semiconductor device, the method comprising:

forming a bottom epitaxy region on a substrate;
forming a semiconductor fin on the bottom epitaxy region;
forming a gate stack over a channel region of the semiconductor fin;
forming a hard mask on a top surface of the semiconductor fin;
forming a conformal liner on the substrate, the gate stack, and the hard mask;
forming a dielectric layer on the conformal liner and on sidewalls of the hard mask, the dielectric layer comprising a first dielectric material;
converting a portion of the dielectric layer to a second dielectric material;
and
exposing the converted portion of the dielectric layer to an etch material;
wherein the etch material removes the first dielectric material at a faster rate than the second dielectric material.

7 more elements

Dependencies are inferred from the claim text.

Method for making VFET devices with ILD protection

Life of this patent

Method for making VFET devices with ILD protection

Life of this patent

Abstract

Claims13