Semiconductor apparatus related to the repairing of a redundancy region
AssigneeSK hynix Inc.
InventorKeun Sik Ko
Life of this patent
Estimating the term…
Abstract
A semiconductor apparatus includes a fuse array, a word line decoder, a bit line decoder, a bank information comparison circuit, and a rupture circuit. The word line decoder is configured to select a word line of the fuse array based on a bank select address signal. The bit line decoder is configured to select a bit line of the fuse array based on a fail row address signal. The bank information comparison circuit and the rupture circuit are configured to rupture a fuse coupled to the word line and the bit line when a fail bank address signal and the bank select address signal correspond to each other.
Claims19
A semiconductor apparatus comprising:
- a fuse array;
- a word line decoder configured to select a word line of the fuse array based on a bank select address signal;
- a bit line decoder configured to select a bit line of the fuse array based on a fail row address signal;
- a bank information comparison circuit configured to generate a rupture enable signal by comparing a fail bank address signal with the bank select address signal;
- and
- a rupture circuit configured to rupture a fuse coupled to the selected word line and the selected bit line based on the rupture enable signal.
A semiconductor apparatus comprising:
- a plurality of memory banks each including a normal region and a redundancy region;
- a test circuit configured to test the redundancy region to detect when a defect occurs in a memory cell and generate a fail row address signal and a fail bank address signal based on the detection of the defect;
- and
- a redundancy repair circuit configured to select a fuse of a fuse array based on the fail row address signal and a bank select address signal, and to rupture the selected fuse when the fail bank address signal corresponds to the bank select address signal.
A semiconductor apparatus comprising:
- a word line decoder configured to select a word line based on a bank select address signal;
- a fail row latch circuit configured to sequentially store a plurality of fail row address signals based on an input control signal, and to output the plurality of fail row address signals based on a plurality of output control signals;
- a bit line decoder configured to select a bit line based on the fail row address signal;
- a fail bank latch circuit configured to sequentially store a plurality of fail bank address signals based on the input control signal, and to output the plurality of fail bank address signals based on the plurality of output control signals;
- a bank information comparison circuit configured to generate a rupture enable signal by comparing the fail bank address signal output from the fail bank latch circuit with the bank select address signal;
- and
- a rupture circuit configured to rupture a fuse coupled to the selected word line and the selected bit line based on the rupture enable signal.
Dependencies are inferred from the claim text.