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AssigneeQUALCOMM Incorporated
InventorsThomas Philip Speier, Viren Ramesh Patel, Michael Phan, Manish Garg, Kevin Magill, Paul Steinmetz, Clint Mumford, Kshitiz Saxena
Estimating the term…
Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.
A memory controller of a processor-based device for efficiently handling memory array failures, configured to:
A memory controller of a processor-based device for efficiently handling memory array failures, comprising:
A method for efficiently handling memory array failures, comprising:
A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to:
Dependencies are inferred from the claim text.