On demand data stream controller for programming and executing operations in an integrated circuit
AssigneeCadence Design Systems, Inc.
InventorsCarl Alexander Wisnesky, II, Patrick Wayne Gallagher, Steven Lee Gregor, Norman Robert Card
Life of this patent
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Abstract
Embodiments relate generally to a scalable, modularized mechanism which allows for storing programmable data streams on chip and provides repeatable on-demand issuances of data streams to one or more targeted instruments. In some embodiments, multiple data streams are grouped into data stream schedules to perform a series of programmable operations on demand. In these and other embodiments, data stream schedules can be reused and further grouped into data stream plans that can be executed in any order upon request or are hard-coded in a specific order.
Claims19
An apparatus comprising:
- a target of a defined operation, wherein the target is a hardware component of an integrated circuit;
- a controller, wherein the controller is also a hardware component and is located within the integrated circuit together with the target, the controller including:
- a store containing a complete set of data for enabling the target to perform the defined operation, and
- a finite state machine that is configured to cause the complete set of data to be sent to the target from the store in a response to a signal for commencing the defined operation;
- a second controller, also located within a same integrated circuit with the target, the second controller including a second store containing the same complete set of data as contained in the store of the controller;
- and
- an error detector for receiving the data from both the controller and the second controller and for detecting an error in the data.
An apparatus comprising:
- a first target of a first defined operation;
- a second target of a second defined operation, wherein the first and second targets are hardware components of an integrated circuit;
- and
- a controller, wherein the controller is also a hardware component and is located within the integrated circuit together with the first and second targets, the controller including:
- a store containing a complete set of data for enabling the first and second targets to perform the first and second defined operations, and
- a finite state machine that is configured to cause the complete set of data to be sent from the store to the first and second targets in a response to a signal for commencing the first and second defined operations,
- wherein the data includes a target ID that allows the first and second target to identify a portion of the data associated with the first and second defined operations, respectively.
A method comprising:
- identifying a defined operation for a target in an integrated circuit, wherein the target is a hardware component of the integrated circuit;
- identifying a complete set of data for enabling the target to perform the defined operation;
- locating a controller as a hardware component in the integrated circuit together with the target;
- configuring the controller to include a store containing the complete set of data and a finite state machine for causing the complete set of data to be sent from the store to the target in a response to a signal for commencing the defined operation,
- locating a second controller within the same integrated circuit with the target and the controller;
- configuring the second controller to include a second store containing the same complete set of data as contained in the store of the controller;
- and
- configuring an error detector to receive the data from both the controller and the second controller and to detect an error in the data.
Dependencies are inferred from the claim text.