Semiconductor device

A semiconductor device comprising:

• a memory cell array with a plurality of memory cells arranged in a matrix, the plurality of memory cells including a first memory cell in a first memory cell column and a second memory cell in a second memory cell column adjacent to the first memory cell column;
• a plurality of bit-line pairs provided for each memory cell column in the memory cell array;
• a plurality of input/output circuits provided respectively corresponding to the bit-line pairs, the plurality of input/output circuits including a first input/output circuit corresponding to the first memory cell column and a second input/output circuit corresponding to the second memory cell column;
• and
• an interface control circuit controlling a data input/output to the input/output circuits when executing data write and data read to each memory cell row in a normal mode,
• wherein the interface control circuit comprises a selection circuit selecting, according to a test address, a data input/output to one of the first input/output circuit and the second input/output circuit alternately when executing the data write and data read to each memory cell row in a test mode.