Shift register circuit, driving method thereof, gate drive circuit, display panel and display device

A shift register circuit comprising:

• a set circuit configured to, responsive to an input pulse from a signal input terminal being active, transfer the input pulse to a first node to set the first node at an active potential;
• a first reset circuit configured to transfer a first reference voltage from a first reference voltage terminal to the first node to set the first node at an inactive potential in response to a reset pulse from a reset signal terminal being active, and to transfer the first reference voltage from the first reference voltage terminal to a signal output terminal in response to the reset pulse from the reset signal terminal being active;
• an output circuit configured to transfer a first clock signal from a first clock signal terminal to the signal output terminal in response to the first node being at the active potential, and to change the active potential at the first node further away from the inactive potential in response to the first clock signal transferred to the signal output terminal being active;
• and
• a first control circuit configured to maintain the first node at the active potential in response to the input pulse from the signal input terminal being active, and to restrict a change in the active potential at the first node based on a second reference voltage from a second reference voltage terminal in response to the first clock signal transferred to the signal output terminal being active, the second reference voltage having a magnitude between a magnitude of the active input pulse and the inactive potential.