Back to results
US 10,541,037 B2Granted
Non-volatile memory with countermeasure for program disturb including delayed ramp down during program verify
AssigneeSanDisk Technologies LLC
InventorsDengtao Zhao, Deepanshu Dutta
Life of this patent
Estimating the term…
Abstract
Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
Claims18
An apparatus, comprising:
- a plurality of non-volatile memory cells;
- control lines connected to the memory cells;
- a write circuit connected to the control lines and configured to write data to selected memory cells by applying a program voltage to a selected control line;
- a verify circuit connected to the control lines;
- and
- a temperature sensing circuit in communication with the verify circuit the verify circuit configured to verify writing of data to the selected memory cells by applying non-zero voltages to the control lines and sensing the selected memory cells;
- and
- the verify circuit further configured to ramp down the voltages on the control lines after the sensing;
- wherein in response to a temperature sensed by the temperature sensing circuit being below a trigger temperature, the verify circuit is configured to ramp down the voltages on the control lines after the sensing, such that an unselected control line adjacent to the selected control line and connected to already programmed memory cells is ramped down subsequent to ramping down the selected control line and one or more other ones of the control lines.
6 more elements
A method comprising:
- programming memory cells connected to a selected control line, the memory cells are part of a memory array;
- applying a verify compare voltage to the selected control line;
- applying bypass voltages to unselected control lines connected to the memory array;
- sensing the memory cells connected to the selected control line in response to the verify compare voltage;
- sensing a temperature;
- lowering the selected control line from the verify compare voltage to ground;
- lowering the unselected control lines from the bypass voltages to ground;
- and
- determining that the temperature is below a trigger temperature, and in response thereto, the lowering the unselected control lines from the bypass voltage to ground includes commencing lowering to ground source side unselected control lines adjacent to the selected control line subsequent to commencing lowering drain side unselected control lines.
6 more elements
An apparatus, comprising:
- a first plurality of connected non-volatile memory cells;
- a plurality of control lines connected to the first plurality of connected non-volatile memory cells;
- and
- a control circuit connected to the control lines;
- and
- a temperature sensor circuit configured to sense a temperature and in communication with the control circuit;
- the control circuit configured to verify programming of a selected memory cell of the first plurality of connected non-volatile memory cells that is connected to a selected control line by applying voltages to the plurality of control lines, sensing the selected memory cell, and ramping down the voltages on the control lines after performing the sensing;
- and
- wherein in response to the temperature sensed by the temperature sensor circuit being below a trigger temperature, the control circuit is configured to perform the ramping down such that an unselected control line adjacent to the selected control line and connected to already programmed memory cells is ramped down subsequent to ramping down the selected word line and another unselected control line connected to already programmed memory cells and a control line connected to not yet programmed memory cells.
6 more elements
An apparatus, comprising:
- a monolithic three dimensional memory array comprising a lower set of alternating conductive and dielectric layers and an upper set of alternating conductive and dielectric layers separated by a joint area that together form a plurality of word lines and a plurality of vertical charge-trapping NAND strings each having a channel;
- means for programming a selected memory cell connected to a selected word line;
- means for sensing a temperature;
- and
- means for verifying programming of the selected memory cell by applying a compare voltage to the selected word line and bypass voltages to unselected word line lines, sensing the selected memory cell in response to the compare voltage, lowering the selected word line from the compare voltage to ground, and lowering the unselected word lines from the bypass voltages to ground;
- wherein in response to the sensed temperature being below a trigger temperature, the means for verifying programming lowers the unselected word lines from the bypass voltages to ground such that a source side unselected word line adjacent to the selected word line and on a drain side of the joint area is lowered to ground subsequent to lowering drain side word lines to ground.
3 more elements
Dependencies are inferred from the claim text.